C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 206

• Manufacturer Part Number: C8051F020DK
• Description: DEV KIT FOR F020/F021/F022/F023
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F020
• Silicon Family Name: C8051F02x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F020/021/022/023
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1200

C8051F020/1/2/3
20.1. UART0 Operational Modes
UART0 provides four operating modes (one synchronous and three asynchronous) selected by setting configuration
bits in the SCON0 register. These four modes offer different baud rates and communication protocols. The four
modes are summarized in Table 20.1.
20.1.1. Mode 0: Synchronous Mode
Mode 0 provides synchronous, half-duplex communication. Serial data is transmitted and received on the RX0 pin.
The TX0 pin provides the shift clock for both transmit and receive. The MCU must be the master since it generates
the shift clock for transmission in both directions (see the interconnect diagram in Figure 20.2).
Data transmission begins when an instruction writes a data byte to the SBUF0 register. Eight data bits are transferred
LSB first (see the timing diagram in Figure 20.3), and the TI0 Transmit Interrupt Flag (SCON0.1) is set at the end of
the eighth bit time. Data reception begins when the REN0 Receive Enable bit (SCON0.4) is set to logic 1 and the RI0
Receive Interrupt Flag (SCON0.0) is cleared. One cycle after the eighth bit is shifted in, the RI0 flag is set and recep-
tion stops until software clears the RI0 bit. An interrupt will occur if enabled when either TI0 or RI0 are set.
The Mode 0 baud rate is SYSCLK / 12. RX0 is forced to open-drain in Mode 0, and an external pull-up will typically
be required.
206
Mode
0
1
2
3
Synchronization
RX (data out)
Asynchronous
Asynchronous
Asynchronous
RX (data in)
Synchronous
TX (clk out)
TX (clk out)
C8051Fxxx
Figure 20.3. UART0 Mode 0 Timing Diagram
Figure 20.2. UART0 Mode 0 Interconnect
D0
Table 20.1. UART0 Modes
D0
SYSCLK / 32 or SYSCLK / 64
RX
TX
Timer 1 or 2 Overflow
Timer 1 or 2 Overflow
D1
D1
SYSCLK / 12
MODE 0 TRANSMIT
Baud Clock
MODE 0 RECEIVE
Rev. 1.4
D2
D2
D3
D3
CLK
DATA
D4
8 Extra Outputs
D4
D5
D5
Data Bits Start/Stop Bits
Reg.
Shift
D6
8
8
9
9
D6
D7
D7
1 Start, 1 Stop
1 Start, 1 Stop
1 Start, 1 Stop
None