C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 258
![DEV KIT FOR F020/F021/F022/F023](/photos/9/23/92314/c8051f020dk_sml.jpg)
C8051F020DK
Manufacturer Part Number
C8051F020DK
Description
DEV KIT FOR F020/F021/F022/F023
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F020DK.pdf
(272 pages)
Specifications of C8051F020DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F020
Silicon Family Name
C8051F02x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F020/021/022/023
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1200
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F020DK
Manufacturer:
SiliconL
Quantity:
10
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C8051F020/1/2/3
23.2.6. 16-Bit Pulse Width Modulator Mode
Each PCA0 module may also be operated in 16-Bit PWM mode. In this mode, the 16-bit capture/compare module
defines the number of PCA0 clocks for the low time of the PWM signal. When the PCA0 counter matches the module
contents, the output on CEXn is asserted high; when the counter overflows, CEXn is asserted low. To output a vary-
ing duty cycle, new value writes should be synchronized with PCA0 CCFn match interrupts. 16-Bit PWM Mode is
enabled by setting the ECOMn, PWMn, and PWM16n bits in the PCA0CPMn register. For a varying duty cycle,
CCFn should also be set to logic 1 to enable match interrupts. The duty cycle for 16-Bit PWM Mode is given by
Equation 23.3.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/Compare
registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit to ‘0’; writing to
PCA0CPHn sets ECOMn to ‘1’
Using Equation 23.3, the largest duty cycle is 100% (PCA0CPn = 0), and the smallest duty cycle is 0.0015%
(PCA0CPn = 0xFFFF). A 0% duty cycle may be generated by clearing the ECOMn bit to ‘0’.
258
W
M
P
1
6
n
1
PCA0CPMn
C
O
M
E
n
C
A
P
P
n
0 0 0 0
C
A
P
N
n
M
A
T
n
PCA Timebase
O
G
T
n
W
P
M
n
E
C
C
F
n
0
Enable
PCA0CPHn
Equation 23.3. 16-Bit PWM Duty Cycle
PCA0H
Figure 23.9. PCA 16-Bit PWM Mode
DutyCycle
16-bit Comparator
PCA0CPLn
PCA0L
=
Rev. 1.4
---------------------------------------------------- -
65536 PCA0CPn
Overflow
–
65536
match
S
R
SET
CLR
Q
Q
CEXn
Crossbar
Port I/O
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