C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 172

• Manufacturer Part Number: C8051F020DK
• Description: DEV KIT FOR F020/F021/F022/F023
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F020
• Silicon Family Name: C8051F02x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F020/021/022/023
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1200

C8051F020/1/2/3
172
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
WEAKPUD XBARE
R/W
Bit7
WEAKPUD: Weak Pull-Up Disable Bit.
0: Weak pull-ups globally enabled.
1: Weak pull-ups globally disabled.
XBARE: Crossbar Enable Bit.
0: Crossbar disabled. All pins on Ports 0, 1, 2, and 3, are forced to Input mode.
1: Crossbar enabled.
UNUSED. Read = 0, Write = don't care.
T4EXE: T4EX Input Enable Bit.
0: T4EX unavailable at Port pin.
1: T4EX routed to Port pin.
T4E: T4 Input Enable Bit.
0: T4 unavailable at Port pin.
1: T4 routed to Port pin.
UART1E: UART1 I/O Enable Bit.
0: UART1 I/O unavailable at Port pins.
1: UART1 TX and RX routed to 2 Port pins.
EMIFLE: External Memory Interface Low-Port Enable Bit.
0: P0.7, P0.6, and P0.5 functions are determined by the Crossbar or the Port latches.
1: If EMI0CF.4 = ‘0’ (External Memory Interface is in Multiplexed mode)
1: If EMI0CF.4 = ‘1’ (External Memory Interface is in Non-multiplexed mode)
CNVSTE: External Convert Start Input Enable Bit.
0: CNVSTR unavailable at Port pin.
1: CNVSTR routed to Port pin.
R/W
Bit6
P0.7 (/WR), P0.6 (/RD), and P0.5 (ALE) are ‘skipped’ by the Crossbar and their output
states are determined by the Port latches and the External Memory Interface.
P0.7 (/WR) and P0.6 (/RD) are ‘skipped’ by the Crossbar and their output states are
determined by the Port latches and the External Memory Interface.
Figure 17.9. XBR2: Port I/O Crossbar Register 2
R/W
Bit5
-
T4EXE
R/W
Bit4
Rev. 1.4
T4E
R/W
Bit3
UART1E
R/W
Bit2
EMIFLE
R/W
Bit1
CNVSTE
R/W
Bit0
SFR Address:
00000000
Reset Value
0xE3