C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 33
![DEV KIT FOR F020/F021/F022/F023](/photos/9/23/92314/c8051f020dk_sml.jpg)
C8051F020DK
Manufacturer Part Number
C8051F020DK
Description
DEV KIT FOR F020/F021/F022/F023
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F020DK.pdf
(272 pages)
Specifications of C8051F020DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F020
Silicon Family Name
C8051F02x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F020/021/022/023
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1200
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F020DK
Manufacturer:
SiliconL
Quantity:
10
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4.
MONEN
VREFD
XTAL1
XTAL2
VREFA
VREF0
VREF1
DGND
AGND
Name
VREF
VDD
/RST
TMS
TCK
TDO
AV+
TDI
PINOUT AND PACKAGE DEFINITIONS
37, 64,
38, 63,
11, 14
10, 13
F020
F022
Pin Numbers
90
89
26
27
28
12
16
17
15
1
2
3
4
5
24, 41,
25, 40,
F021
F023
57
56
58
59
60
61
62
17
18
19
6
5
7
8
D Out JTAG Test Data Output with internal pull-up. Data is shifted out on
A Out Crystal Output. This pin is the excitation driver for a crystal or
D I/O Device Reset. Open-drain output of internal VDD monitor. Is driven
A I/O Bandgap Voltage Reference Output (all devices).
Type
D In
D In
D In
A In
D In
A In
A In
A In
A In
Table 4.1. Pin Definitions
Description
Digital Supply Voltage. Must be tied to +2.7 to +3.6 V.
Digital Ground. Must be tied to Ground.
Analog Supply Voltage. Must be tied to +2.7 to +3.6 V.
Analog Ground. Must be tied to Ground.
JTAG Test Mode Select with internal pull-up.
JTAG Test Clock with internal pull-up.
JTAG Test Data Input with internal pull-up. TDI is latched on the
rising edge of TCK.
TDO on the falling edge of TCK. TDO output is a tri-state driver.
low when VDD is <2.7 V and MONEN is high. An external source
can initiate a system reset by driving this pin low.
Crystal Input. This pin is the return for the internal oscillator circuit
for a crystal or ceramic resonator. For a precision internal clock,
connect a crystal or ceramic resonator from XTAL1 to XTAL2. If
overdriven by an external CMOS clock, this becomes the system
clock.
ceramic resonator.
VDD Monitor Enable. When tied high, this pin enables the internal
VDD monitor, which forces a system reset when VDD is < 2.7 V.
When tied low, the internal VDD monitor is disabled.
DAC Voltage Reference Input (F021/3 only).
ADC0 and ADC1 Voltage Reference Input.
ADC0 Voltage Reference Input.
ADC1 Voltage Reference Input.
DAC Voltage Reference Input.
Rev. 1.4
C8051F020/1/2/3
33
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