C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 174

• Manufacturer Part Number: C8051F020DK
• Description: DEV KIT FOR F020/F021/F022/F023
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F020
• Silicon Family Name: C8051F02x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F020/021/022/023
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1200

C8051F020/1/2/3
174
Bits7-0:
Notes:
1.
2.
Bits7-0:
P1.7
R/W
R/W
Bit7
Bit7
P1.[7:0]: Port1 Output Latch Bits.
(Write - Output appears on I/O pins per XBR0, XBR1, XBR2, and XBR3 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P1MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, XBR2, and XBR3 Register settings).
0: P1.n pin is logic low.
1: P1.n pin is logic high.
P1.[7:0] can be configured as inputs to ADC1 as AIN1.[7:0], in which case they are ‘skipped’ by the
Crossbar assignment process and their digital input paths are disabled, depending on P1MDIN (See
Figure 17.13). Note that in analog mode, the output mode of the pin is determined by the Port 1 latch
and P1MDOUT (Figure 17.14). See
tion about ADC1.
P1.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Non-multiplexed
mode). See
on page 145
P1MDIN.[7:0]: Port 1 Input Mode Bits.
0: Port Pin is configured in Analog Input mode. The digital input path is disabled (a read from the
Port bit will always return ‘0’). The weak pull-up on the pin is disabled.
1: Port Pin is configured in Digital Input mode. A read from the Port bit will return the logic level at
the Pin. The state of the weak pull-up is determined by the WEAKPUD bit (XBR2.7, see
Figure 17.9).
P1.6
R/W
R/W
Bit6
Bit6
Section “16. EXTERNAL DATA MEMORY INTERFACE AND ON-CHIP XRAM”
Figure 17.13. P1MDIN: Port1 Input Mode Register
for more information about the External Memory Interface.
P1.5
R/W
R/W
Bit5
Bit5
Figure 17.12. P1: Port1 Data Register
P1.4
R/W
R/W
Bit4
Bit4
Section “7. ADC1 (8-Bit ADC)” on page 75
Rev. 1.4
P1.3
R/W
R/W
Bit3
Bit3
P1.2
R/W
R/W
Bit2
Bit2
P1.1
R/W
R/W
Bit1
Bit1
(bit addressable)
P1.0
R/W
R/W
Bit0
Bit0
for more informa-
SFR Address:
SFR Address:
Reset Value
11111111
Reset Value
11111111
0xBD
0x90