C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 201
![DEV KIT FOR F020/F021/F022/F023](/photos/9/23/92314/c8051f020dk_sml.jpg)
C8051F020DK
Manufacturer Part Number
C8051F020DK
Description
DEV KIT FOR F020/F021/F022/F023
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F020DK.pdf
(272 pages)
Specifications of C8051F020DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F020
Silicon Family Name
C8051F02x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F020/021/022/023
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1200
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F020DK
Manufacturer:
SiliconL
Quantity:
10
- Current page: 201 of 272
- Download datasheet (2Mb)
19.4. SPI Special Function Registers
SPI0 is accessed and controlled through four special function registers in the system controller: SPI0CN Control Reg-
ister, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock Rate Register. The four special
function registers related to the operation of the SPI0 Bus are described in the following section.
Bit7:
Bit6:
Bits5-3:
Bits2-0:
CKPHA
R/W
Bit7
CKPHA: SPI0 Clock Phase.
This bit controls the SPI0 clock phase.
0: Data sampled on first edge of SCK period.
1: Data sampled on second edge of SCK period.
CKPOL: SPI0 Clock Polarity.
This bit controls the SPI0 clock polarity.
0: SCK line low in idle state.
1: SCK line high in idle state.
BC2-BC0: SPI0 Bit Count.
Indicates which of the up to 8 bits of the SPI0 word have been transmitted.
SPIFRS2-SPIFRS0: SPI0 Frame Size.
These three bits determine the number of bits to shift in/out of the SPI0 shift register during a data
transfer in master mode. They are ignored in slave mode.
CKPOL
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
R/W
Bit6
Figure 19.5. SPI0CFG: SPI0 Configuration Register
BC2-BC0
SPIFRS
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
BC2
Bit5
R
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
BC1
Bit4
R
BIT Transmitted
Bits Shifted
Bit 7 (MSB)
Bit 0 (LSB)
BC0
Bit3
R
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Rev. 1.4
1
2
3
4
5
6
7
8
SPIFRS2
R/W
Bit2
SPIFRS1
C8051F020/1/2/3
R/W
Bit1
SPIFRS0
R/W
Bit0
SFR Address:
00000111
Reset Value
0x9A
201
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