C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 241
![DEV KIT FOR F020/F021/F022/F023](/photos/9/23/92314/c8051f020dk_sml.jpg)
C8051F020DK
Manufacturer Part Number
C8051F020DK
Description
DEV KIT FOR F020/F021/F022/F023
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F020DK.pdf
(272 pages)
Specifications of C8051F020DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F020
Silicon Family Name
C8051F02x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F020/021/022/023
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1200
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F020DK
Manufacturer:
SiliconL
Quantity:
10
- Current page: 241 of 272
- Download datasheet (2Mb)
Bit7:
Bits6-3:
Bit2:
Bit1:
Bit0:
Bits 7-0: TMR3RLL: Timer 3 Reload Register Low Byte.
TF3
R/W
R/W
Bit7
Bit7
TF3: Timer3 Overflow Flag.
Set by hardware when Timer 3 overflows from 0xFFFF to 0x0000. When the Timer 3 interrupt is
enabled, setting this bit causes the CPU to vector to the Timer 3 Interrupt service routine. This bit is
not automatically cleared by hardware and must be cleared by software.
UNUSED. Read = 0000b, Write = don't care.
TR3: Timer 3 Run Control.
This bit enables/disables Timer 3.
0: Timer 3 disabled.
1: Timer 3 enabled.
T3M: Timer 3 Clock Select.
This bit controls the division of the system clock supplied to Counter/Timer 3.
0: Counter/Timer 3 uses the system clock divided by 12.
1: Counter/Timer 3 uses the system clock.
T3XCLK: Timer 3 External Clock Select
This bit selects the external oscillator input divided by 8 as the Timer 3 clock source. When T3XCLK
is logic 1, bit T3M (TMR3CN.1) is ignored.
0: Timer 3 clock source defined by bit T3M (TMR3CN.1).
1: Timer 3 clock source is the external oscillator input divided by 8.
Timer 3 is configured as an auto-reload timer. This register holds the low byte of the reload value.
R/W
R/W
Bit6
Figure 22.21. TMR3RLL: Timer 3 Reload Register Low Byte
Bit6
-
Figure 22.20. TMR3CN: Timer 3 Control Register
R/W
R/W
Bit5
Bit5
-
R/W
R/W
Bit4
Bit4
-
R/W
R/W
Bit3
Bit3
-
Rev. 1.4
TR3
R/W
R/W
Bit2
Bit2
T3M
C8051F020/1/2/3
R/W
R/W
Bit1
Bit1
T3XCLK
R/W
R/W
Bit0
Bit0
SFR Address:
SFR Address:
00000000
00000000
Reset Value
Reset Value
0x91
0x92
241
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