C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 151
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C8051F020DK
Manufacturer Part Number
C8051F020DK
Description
DEV KIT FOR F020/F021/F022/F023
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F020DK.pdf
(272 pages)
Specifications of C8051F020DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F02x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F020
Silicon Family Name
C8051F02x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
Silicon Laboratories C8051 F020/021/022/023
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1200
Available stocks
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Part Number
Manufacturer
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Price
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Part Number:
C8051F020DK
Manufacturer:
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16.5.3. Split Mode with Bank Select
When EMI0CF.[3:2] are set to ‘10’, the XRAM memory map is split into two areas, on-chip space and off-chip space.
•
•
•
•
16.5.4. External Only
When EMI0CF[3:2] are set to ‘11’, all MOVX operations are directed to off-chip space. On-chip XRAM is not visi-
ble to the CPU. This mode is useful for accessing off-chip memory located between 0x0000 and the 4k boundary.
•
•
16.6. Timing
The timing parameters of the External Memory Interface can be configured to enable connection to devices having
different setup and hold time requirements. The Address Setup time, Address Hold time, /RD and /WR strobe widths,
and in multiplexed mode, the width of the ALE pulse are all programmable in units of SYSCLK periods through
EMI0TC, shown in Figure 16.6, and EMI0CF[1:0].
The timing for an off-chip MOVX instruction can be calculated by adding 4 SYSCLK cycles to the timing parameters
defined by the EMI0TC register. Assuming non-multiplexed operation, the minimum execution time for an off-chip
XRAM operation is 5 SYSCLK cycles (1 SYSCLK for /RD or /WR pulse + 4 SYSCLKs). For multiplexed opera-
tions, the Address Latch Enable signal will require a minimum of 2 additional SYSCLK cycles. Therefore, the mini-
mum execution time of an off-chip XRAM operation in multiplexed mode is 7 SYSCLK cycles (2 SYSCLKs for
/ALE, 1 for /RD or /WR + 4 SYSCLKs). The programmable setup and hold times default to the maximum delay set-
tings after a reset.
Table 16.1 lists the AC parameters for the External Memory Interface, and Figure 16.7 through Figure 16.11 show the
timing diagrams for the different External Memory Interface modes and MOVX operations
Effective addresses below the 4k boundary will access on-chip XRAM space.
Effective addresses beyond the 4k boundary will access off-chip space.
8-bit MOVX operations use the contents of EMI0CN to determine whether the memory access is on-chip or off-
chip. The upper 8-bits of the Address Bus A[15:8] are determined by EMI0CN, and the lower 8-bits of the
Address Bus A[7:0] are determined by R0 or R1. All 16-bits of the Address Bus A[15:0] are driven in “Bank
Select” mode.
16-bit MOVX operations use the contents of DPTR to determine whether the memory access is on-chip or off-
chip, and the full 16-bits of the Address Bus A[15:0] are driven during the off-chip transaction.
8-bit MOVX operations ignore the contents of EMI0CN. The upper Address bits A[15:8] are not driven (identi-
cal behavior to an off-chip access in “Split Mode without Bank Select” described above). This allows the user to
manipulate the upper address bits at will by setting the Port state directly. The lower 8-bits of the effective
address A[7:0] are determined by the contents of R0 or R1.
16-bit MOVX operations use the contents of DPTR to determine the effective address A[15:0]. The full 16-bits
of the Address Bus A[15:0] are driven during the off-chip transaction.
Rev. 1.4
C8051F020/1/2/3
151
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