C8051F020DK Silicon Laboratories Inc, C8051F020DK Datasheet - Page 26

• Manufacturer Part Number: C8051F020DK
• Description: DEV KIT FOR F020/F021/F022/F023
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F020DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051F02x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F020
• Silicon Family Name: C8051F02x
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: Silicon Laboratories C8051 F020/021/022/023
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1200

C8051F020/1/2/3
1.4.
The standard 8051 Ports (0, 1, 2, and 3) are available on the MCUs. The C8051F020/2 have 4 additional ports (4, 5,
6, and 7) for a total of 64 general-purpose port I/O. The Port I/O behave like the standard 8051 with a few enhance-
ments.
Each Port I/O pin can be configured as either a push-pull or open-drain output. Also, the "weak pull-ups" which are
normally fixed on an 8051 can be globally disabled, providing additional power saving capabilities for low-power
applications.
Perhaps the most unique enhancement is the Digital Crossbar. This is essentially a large digital switching network
that allows mapping of internal digital system resources to Port I/O pins on P0, P1, P2, and P3. (See Figure 1.9)
Unlike microcontrollers with standard multiplexed digital I/O, all combinations of functions are supported.
The on-chip counter/timers, serial buses, HW interrupts, ADC Start of Conversion input, comparator outputs, and
other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar Con-
trol registers. This allows the user to select the exact mix of general purpose Port I/O and digital resources needed for
the particular application.
26
Highest
Priority
Lowest
Priority
Latches
Port
Programmable Digital I/O and Crossbar
/SYSCLK
CNVSTR
T2, T2EX,
T4,T4EX
Comptr.
Outputs
UART0
UART1
SMBus
T0, T1,
/INT0,
/INT1
PCA
P0
P1
P2
P3
SPI
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
(P3.0-P3.7)
8
8
8
8
2
4
2
2
6
2
8
Figure 1.9. Digital Crossbar Diagram
XBR2, P1MDIN
XBR0, XBR1,
Crossbar
Rev. 1.4
Decoder
To External
Registers
Priority
Digital
Interface
Memory
(EMIF)
8
8
8
8
P0MDOUT, P1MDOUT,
P2MDOUT, P3MDOUT
Registers
ADC1
Input
Cells
Cells
Cells
Cells
To
P0
I/O
P1
I/O
P2
I/O
P3
I/O
External
Pins
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0
P3.7
Highest
Lowest
Priority
Priority