MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1064
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MPC8536E-ANDROID
Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr
Datasheets
1.MPC8536EBVTAVLA.pdf
(127 pages)
2.MPC8536EBVTAVLA.pdf
(2 pages)
3.MPC8536EBVTAVLA.pdf
(1706 pages)
Specifications of MPC8536E-ANDROID
Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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PCI Bus Interface
16.3.2.12 PCI Subsystem Vendor ID Register
The PCI subsystem vendor ID register is used to identify the subsystem.
16-38
Offset 0x2C
Reset
Offset 0x1C
Reset
31–12 ADDRESS Indicates the base address that the inbound memory window resides at. The number of upper bits
31–0 ADDRESS Indicates the base address that the inbound memory window resides at. The number of upper bits
Bits
11–4
Bits
2–1
W
3
0
R
W
R
0x24
15–0
31
15
Bits
Name
Name
PREF
TYPE
MSI
—
Table 16-36. 64-Bit Low Memory Base Address Register Field Descriptions
Table 16-37. Bit Setting for 64-Bit High Memory Base Address Register
Subsystem Vendor ID 0x0000
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
that the device allows to be writable is selected through the inbound translation windows. If no
access to local memory is to be permitted by external masters then all bits are programmed.
that the device allows to be writable is selected through the inbound translation windows.
Reserved. The device allows a 4 Kbyte window minimum.
Prefetchable
Type.
10 Locate anywhere in 64-bit address space.
Memory space indicator
Table 16-38. PCI Subsystem Vendor ID Register Field Description
Figure 16-38. 64-Bit High Memory Base Address Register
Name
Figure 16-39. PCI Subsystem Vendor ID Register
Subsystem Vendor ID
ADDRESS
All zeros
All zeros
Description
Description
Description
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
0
0
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