MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1119
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MPC8536E-ANDROID
Manufacturer Part Number
MPC8536E-ANDROID
Description
HARDWARE/SOFTWARE ANDROID OS
Manufacturer
Freescale Semiconductor
Series
PowerQUICC ™r
Type
MPUr
Datasheets
1.MPC8536EBVTAVLA.pdf
(127 pages)
2.MPC8536EBVTAVLA.pdf
(2 pages)
3.MPC8536EBVTAVLA.pdf
(1706 pages)
Specifications of MPC8536E-ANDROID
Contents
Board
For Use With/related Products
MPC8536
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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- Download datasheet (15Mb)
Figure 17-18
Table 17-18
Freescale Semiconductor
Offset Window 1: 0xC30
Reset 0
8–10
Bits
1–2
5–7
11
0
3
4
W
R
Window 2: 0xC50
Window 3: 0xC70
Window 4: 0xC90
EN
0
Name
ROE
EN
NS
TC
—
—
—
Figure 17-18. PCI Express Outbound Window Attributes Registers 1–4 (PEXOWAR n )
—
0
1
describes the fields of the PCI Express outbound window attributes registers.
shows the PCI Express outbound window attributes registers 1–4 (PEXOWARn).
Enable. This bit enables this address translation window. For the default window, this bit is read-only and
always hardwired to 1.
0 Disable outbound translation window
1 Enable outbound translation window
Reserved
Relaxed ordering enable. This bit when set and the PCI Express device control register[Enable Relaxed] bit
is set enables the Relaxed Ordering bit for the packet. This bit only applies to memory transactions.
0 Default ordering
1 Relaxed ordering
No snoop enable. This bit when set and the PCI Express device control register[Enable No Snoop] bit is set
enables the no snoop bit for the packet. This bit only applies to memory transactions.
0 Snoopable
1 No snoop
Reserved
Traffic class. This field indicates the traffic class of the outbound packet. This field only applies to memory
transaction. All other transaction types should set the TC field to 0.
000 TC0
001 TC1
010 TC2
011 TC3
100 TC4
101 TC5
110 TC6
111 TC7
Note: Traffic class settings are passed through to the PCI Express link, but no specific actions are taken in
Reserved
0
2
ROE NS
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
3
the device based on traffic class.
0
4
0
5
0
Table 17-18. PEXOWAR n Field Descriptions
7
0
8
0
TC
0
10 11 12
0
0
0
1
RTT
Description
0
15 16
0
0
WTT
1
0
19 20
0
0 0 0 0 0 0
—
PCI Express Interface Controller
25 26
1
Access: Read/Write
0
OWS
0 0
17-23
1
31
1
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