MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 252

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

L2 Look-Aside Cache/SRAM
6.8.1
PLRU bit updates depend on which cache way was last accessed, as summarized in
When an L2 line is invalidated, the PLRU bits are updated, marking the corresponding way as
least-recently used. This causes the invalidated way to be selected as the next victim.
6.8.2
The general PLRU algorithm described above must be modified to take into account special features of
the L2 cache; namely SRAM regions, line locking, and stash-only regions. Each of these features reserves
ways within each cache set such that some ways are not eligible for allocation/victimization by the general
LRU algorithm.
To preserve the state of the ways that are set aside for other special functions, the PLRU pointers are
modified by a mask that is a function of the L2 configuration registers, the lock bits in the cache status
array, and initiator of the transaction. The mask effectively points the PLRU algorithm away from ways
that are not to be considered for replacement.
L2 cache lines are locked through the status array lock bits. There are two lock bits for each way of each
set (1024 sets by eight ways). These bits are set or cleared through special L2 controller commands.There
are two sets of lock bits, one for instructions (I0–I7) and one for data (D0–D7) for every line. The lock bits
act as a mask over the PLRU bits to determine victim selection. The PLRU bits are updated regardless of
line locking.
Lock bits are used at allocate time to steer the PLRU algorithm away from selecting locked victims. In the
following discussion, the eight lock bits for a particular set are called L0–L7.
An effective value of each PLRU bit is calculated as follows:
6-32
Where Lock Way i: Li = Di | Ii, i=0…7 (Di = data lock, Ii = instruction lock)
P0_eff = f(P0,L0,L1,L2,L3,L4,L5,L6,L7) = (L0 & L1 & L2 & L3) | (P0 & ~(L4 & L5 & L6 & L7))
P1_eff = f(P1,L0,L1,L2,L3) = (L0 & L1) | (P1 & ~(L2 & L3))
P2_eff = f(P2,L4,L5,L6,L7) = (L4 & L5) | (P2 & ~(L6 & L7))
PLRU Bit Update Considerations
Allocation of Lines
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 6-24. PLRU Bit Update Algorithm
Accessed
Last Way
0
1
2
3
4
5
6
7
P0 P1 P2 P3 P4 P5 P6
1
1
1
1
0
0
0
0
—
—
—
—
1
1
0
0
—
—
—
—
PLRU Bits
1
1
0
0
—
—
—
—
—
—
1
0
—
—
—
—
—
—
1
0
—
—
—
—
—
—
1
0
—
—
—
—
—
—
1
0
Freescale Semiconductor
Table
6-24.