MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 898

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
A TBI interface has 26 signals (GE_GTX_CLK125 included) for connecting to an Ethernet PHY, as
defined by IEEE 802.3z GMII and TBI standards.
14.6.1.6
This section describes the reduced ten-bit interface (RTBI) intended to be used between the PHYs and the
eTSEC to implement a reduced-pin count version of a SerDes interface for optical-fiber devices in
1000BASE-SX/LX applications.
signals required to establish eTSEC module connection with a PHY. Note that in RTBI the eTSEC
immediately begins auto-negotiation with the SerDes.
14-150
1
The management signals (MDC and MDIO) are common to all of the Ethernet controllers’
connections in the system, assuming that each PHY has a different management address.
eTSEC
Reduced Ten-Bit Interface (RTBI)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Gigabit Transmit Clock (TSEC n _GTX_CLK)
Gigabit Reference Clock (GTX_CLK125)
TBI Receive Clock 0 (TSEC n _RX_CLK)
TBI Receive Clock 1 (TSEC n _TX_CLK)
SIGNAL DETECT (TSEC n _RX_CRS)
Figure 14-137
Figure 14-136. eTSEC-TBI Connection
Transmit Data (TSEC n _TXD[9:0])
Receive Data (TSEC n _RXD[9:0])
Management Data Clock
Management Data I/O
depicts the basic components of the RTBI including the
1
1
(MDIO)
(MDC)
Ethernet
Gigabit
PHY
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