MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 345

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13 x 10
13 x 10
8.5.3
The following section describes the commands and timings the controller uses when operating in DDR3
or DDR2 modes.
All read or write accesses to DDR SDRAM are performed by the DDR memory controller using JEDEC
standard DDR SDRAM interface commands. The SDRAM device samples command and address inputs
on rising edges of the memory clock; data is sampled using both the rising and falling edges of DQS. Data
read from the DDR SDRAM is also sampled on both edges of DQS.
The following DDR SDRAM interface commands (summarized in
controller. All actions for these commands are described from the perspective of the SDRAM device.
Freescale Semiconductor
x 3
x 2
•
•
•
•
•
Row
Col
x
MRAS
MCAS
MRAS
MCAS
MBA
MBA
Row activate—Latches row address and initiates memory read of that row. Row data is latched in
SDRAM sense amplifiers and must be restored by a precharge command before another row
activate occurs.
Precharge—Restores data from the sense amplifiers to the appropriate row. Also initializes the
sense amplifiers in preparation for reading another row in the memory array (performing another
activate command). Precharge must occur after read or write, if the row address changes on the
next open page mode access.
Read—Latches column address and transfers data from the selected sense amplifier to the output
buffer as determined by the column address. During each succeeding clock edge, additional data is
driven without additional read commands. The amount of data transferred is determined by the
burst size which defaults to 4.
Write—Latches column address and transfers data from the data pins to the selected sense
amplifier as determined by the column address. During each succeeding clock edge, additional data
is transferred to the sense amplifiers from the data pins without additional write commands. The
amount of data transferred is determined by the data masks and the burst size, which is set to four
by the DDR memory controller.
Refresh (similar to MCAS before MRAS)—Causes a row to be read in all logical banks (JEDEC
SDRAM) as determined by the refresh row address counter. This refresh row address counter is
internal to the SDRAM. After being read, the row is automatically rewritten in the memory array.
All logical banks must be in a precharged state before executing a refresh. The memory controller
Table 8-60. Example of Address Multiplexing for 64-bit Data Bus Interleaving Between
JEDEC Standard DDR SDRAM Interface Commands
msb
4
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33–35
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Two Banks with Partial Array Self Refresh Enabled (continued)
2
1
1
0
0
12 11 10 9
12 11 10 9
8
8
7
7
6
6
Address from Core Master
5
5
4
4
3
3
2
2
1
1
0
0
Table
SEL
SEL
CS
CS
9
9
8-61) are provided by the DDR
8
8
7
7
6
6
5
5
DDR Memory Controller
4
4
3
3
2
2
1
1
0
0
8-71
lsb