MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 22

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
13.4.3.1.3
13.4.3.2
13.4.3.2.1
13.4.3.2.2
13.4.3.2.3
13.4.3.2.4
13.4.3.2.5
13.4.3.3
13.4.3.3.1
13.4.3.3.2
13.4.3.3.3
13.4.3.3.4
13.4.3.3.5
13.4.3.4
13.4.3.4.1
13.4.3.4.2
13.4.4
13.4.4.1
13.4.4.1.1
13.4.4.1.2
13.4.4.1.3
13.4.4.1.4
13.4.4.2
13.4.4.2.1
13.4.4.2.2
13.4.4.3
13.4.4.4
13.4.4.4.1
13.4.4.4.2
13.4.4.4.3
13.4.4.4.4
13.4.4.4.5
13.4.4.4.6
13.4.4.4.7
13.4.4.4.8
13.4.4.4.9
13.4.4.4.10
13.4.4.5
13.4.4.6
13.5
13.5.1
xxii
Initialization/Application Information ......................................................................... 13-90
User-Programmable Machines (UPMs)................................................................... 13-74
Interfacing to Peripherals in Different Address Modes ........................................... 13-90
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Programming FCM.............................................................................................. 13-65
FCM Signal Timing ............................................................................................. 13-68
FCM Boot Chip-Select Operation ....................................................................... 13-72
UPM Requests ..................................................................................................... 13-75
Programming the UPMs ...................................................................................... 13-78
UPM Signal Timing............................................................................................. 13-80
RAM Array .......................................................................................................... 13-80
Synchronous Sampling of LUPWAIT for Early Transfer Acknowledge ............ 13-89
Extended Hold Time on Read Accesses .............................................................. 13-90
Error Correcting Codes and the Spare Region ................................................ 13-63
FCM Command Instructions ........................................................................... 13-66
FCM No-Operation Instruction ....................................................................... 13-66
FCM Address Instructions............................................................................... 13-66
FCM Data Read Instructions ........................................................................... 13-67
FCM Data Write Instructions .......................................................................... 13-67
FCM Chip-Select Timing ................................................................................ 13-68
FCM Command, Address, and Write Data Timing ......................................... 13-68
FCM Ready/Busy Timing................................................................................ 13-70
FCM Read Data Timing .................................................................................. 13-70
FCM Extended Read Hold Timing.................................................................. 13-71
FCM Bank 0 Reset Initialization ..................................................................... 13-72
Boot Block Loading into the FCM Buffer RAM............................................. 13-73
Memory Access Requests................................................................................ 13-76
UPM Refresh Timer Requests ......................................................................... 13-77
Software Requests—RUN Command ............................................................. 13-77
Exception Requests.......................................................................................... 13-77
UPM Programming Example (Two Sequential Writes to the RAM Array).... 13-79
UPM Programming Example (Two Sequential Reads from the RAM Array) 13-79
RAM Words..................................................................................................... 13-80
Chip-Select Signal Timing (CSTn) ................................................................. 13-84
Byte Select Signal Timing (BSTn) .................................................................. 13-84
General-Purpose Signals (GnTn, GOn)........................................................... 13-85
Loop Control (LOOP) ..................................................................................... 13-85
Repeat Execution of Current RAM Word (REDO) ......................................... 13-86
Address Multiplexing (AMX) ......................................................................... 13-86
Data Valid and Data Sample Control (UTA) ................................................... 13-87
LGPL[0:5] Signal Negation (LAST) ............................................................... 13-88
Wait Mechanism (WAEN) ............................................................................... 13-88
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Freescale Semiconductor
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