MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 674

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Local Bus Controller
not set bits. It captures the errors during full page read transfers on FCM command completion event,
provided ECC check is enabled in BRx[DECC].
13.3.1.15 Local Bus Configuration Register (LBCR)
The local bus configuration register (LBCR) is shown in
13-32
Offset 0x0_50D0
Reset
Reset
Offset 0x0_50C4
Reset
12–15
16–27
28–31
0–11
W
W
Bits
R
R
W
R
LDIS
16
0
0
MBUE Multi bit uncorrectable error
Name
SBCE Single bit correctable error
—
—
1
Reserved
There are at most four 512-byte page blocks (for a large page device) checked by ECC. A bit is set for
the 512-byte block that had a single bit correctable ECC error on read (bit 12 represents block 0, the first
512 bytes of a page; if ORx[PGS] = 0, bits 13–15 are always 0).
Reserved
There are at most four 512-byte page blocks (for a large page device) checked by ECC. A bit is set for
the 512-byte block that had an uncorrectable ECC error on read (bit 28 represents block 0, the first 512
bytes of a page; if ORx[PGS] = 0, bits 29–31 are always 0).
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
Figure 13-18. Transfer Error ECC Register (LTECCR)
BMT
Figure 13-19. Local Bus Configuration Register
—
Table 13-21. LTECCR Field Descriptions
11 12
SBCE
23
7
All zeros
All zeros
All zeros
15 16
Description
24
8
Figure
BCTLC
9
13-19.
—
AHD
10
11
27
—
28
—
Freescale Semiconductor
13
BMTPS
Access: Read/Write
27 28
LPBSE EPAR
14
Access: w1c
MBUE
15
31
31