MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 11

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
8.5.11
8.5.12
8.6
8.6.1
8.6.2
8.6.3
8.6.3.1
8.6.3.2
8.6.3.3
9.1
9.1.1
9.1.2
9.1.3
9.1.3.1
9.1.3.2
9.1.4
9.1.4.1
9.1.4.2
9.1.4.3
9.2
9.2.1
9.2.2
9.3
9.3.1
9.3.1.1
9.3.1.2
9.3.1.3
9.3.1.4
9.3.1.5
9.3.1.6
9.3.1.7
9.3.1.8
9.3.2
9.3.2.1
9.3.2.2
Freescale Semiconductor
Initialization/Application Information ........................................................................... 8-87
Introduction...................................................................................................................... 9-1
External Signal Descriptions ........................................................................................... 9-7
Memory Map/Register Definition ................................................................................... 9-9
Error Checking and Correcting (ECC) ...................................................................... 8-84
Error Management ..................................................................................................... 8-86
Programming Differences between Memory Types .................................................. 8-89
DDR SDRAM Initialization Sequence ...................................................................... 8-94
Using Forced Self-Refresh Mode to Implement a Battery-Backed
Overview...................................................................................................................... 9-1
Interrupts to the Processor Core................................................................................... 9-4
Modes of Operation ..................................................................................................... 9-4
Interrupt Sources.......................................................................................................... 9-5
Signal Overview .......................................................................................................... 9-8
Detailed Signal Descriptions ....................................................................................... 9-8
Global Registers......................................................................................................... 9-19
Global Timer Registers .............................................................................................. 9-23
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
RAM System ......................................................................................................... 8-94
Hardware Based Self-Refresh................................................................................ 8-94
Software Based Self-Refresh................................................................................. 8-95
Bypassing Re-initialization During Battery-Backed Operation ............................ 8-95
Mixed Mode (GCR[M] = 1) .................................................................................... 9-5
Pass-Through Mode (GCR[M] = 0) ........................................................................ 9-5
Interrupt Routing—Mixed Mode............................................................................. 9-6
Interrupt Destinations .............................................................................................. 9-6
Internal Interrupt Sources ........................................................................................ 9-6
Block Revision Register 1 (BRR1)........................................................................ 9-19
Block Revision Register 2 (BRR2)........................................................................ 9-19
Feature Reporting Register (FRR)......................................................................... 9-20
Global Configuration Register (GCR)................................................................... 9-21
Vendor Identification Register (VIR) .................................................................... 9-21
Interprocessor Interrupt Vector/Priority Registers (IPIVPR0–IPIVPR3).............. 9-22
Spurious Vector Register (SVR)............................................................................ 9-23
Timer Frequency Reporting Register (TFRRA–TFRRB) ..................................... 9-24
Global Timer Current Count Registers (GTCCRA0–GTCCRA3,
Processor Core Initialization Register (PIR) ......................................................... 9-22
GTCCRB0–GTCCRB3)..................................................................................... 9-24
Programmable Interrupt Controller (PIC)
Contents
Chapter 9
Title
Number
Page
xi