MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1437

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

following field in the siTD is used to track and detect errors in the execution of a split transaction for an
IN isochronous endpoint.
If a transaction translator returns with the final data before all of the complete-splits have been executed,
the state of the transfer is advanced so that the remaining complete-splits are not executed. It is important
to note that an IN siTD is retired based solely on the responses from the transaction translator to the
complete-split transactions. This means, for example, that it is possible for a transaction translator to
respond to a complete-split with an MDATA PID. The number of bytes in the MDATA's data payload could
cause the siTD[Total Bytes to Transfer] field to decrement to zero. This response can occur, before all of
the scheduled complete-splits have been executed. In other interface, data structures (for example,
high-speed data streams through queue heads), the transition of Total Bytes to Transfer to zero signals the
end of the transfer and results in clearing the Active bit. However, in this case, the result has not been
delivered by the transaction translator and the host must continue with the next complete-split transaction
to extract the residual transaction state. This scenario occurs because of the pipeline rules for a transaction
translator. In summary, the periodic pipeline rules require that on a micro-frame boundary, the transaction
translator holds the final two bytes received (if it has not seen an End Of Packet (EOP)) in the full-speed
bus pipe stage and gives the remaining bytes to the high-speed pipeline stage. At the micro-frame
boundary, the transaction translator could have received the entire packet (including both CRC bytes) but
not received the packet EOP. In the next micro-frame, the transaction translator responds with an MDATA
and sends all of the data bytes (with the two CRC bytes being held in the full-speed pipeline stage). This
could cause the siTD to decrement it's Total Bytes to Transfer field to zero, indicating it has received all
expected data. The host must still execute one more (scheduled) complete-split transaction in order to
extract the results of the full-speed transaction from the transaction translator (for example, the transaction
translator may have detected a CRC failure, and this result must be forwarded to the host).
If the host experiences hold-offs that cause the host controller to skip one or more (but not all) scheduled
split transactions for an isochronous OUT, then the protocol to the transaction translator is not consistent
and the transaction translator detects and reacts to the problem. Likewise, for host hold-offs that cause the
host controller to skip one or more (but not all) scheduled split transactions for an isochronous IN, the
C-prog-mask is used by the host controller to detect errors. However, if the host experiences a hold-off that
causes it to skip all of an siTD, or an siTD expires during a host hold off (for example, a hold-off occurs
and the siTD is no longer reachable by the host controller in order for it to report the hold-off event), then
system software must detect that the siTDs have not been processed by the host controller (for example,
state not advanced) and report the appropriate error to the client driver.
Freescale Semiconductor
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C-prog-mask. This is an eight-bit bit-vector where the host controller keeps track of which
complete-splits have been executed. Due to the nature of the transaction translator periodic
pipeline, the complete-splits need to be executed in-order. The host controller needs to detect when
the complete-splits have not been executed in order. This can only occur due to system hold-offs
where the host controller cannot get to the memory-based schedule. C-prog-mask is a simple
bit-vector that the host controller sets a bit for each complete-split executed. The bit position is
determined by the micro-frame (FRINDEX[2–0]) number in which the complete-split was
executed. The host controller always checks C-prog-mask before executing a complete-split
transaction. If the previous complete-splits have not been executed, then it means one (or more)
have been skipped and data has potentially been lost. System software is required to initialize this
field to zero before setting an siTD's Active bit to a one.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Universal Serial Bus Interfaces
21-103