MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 526

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.7.2.8
The end of message register in the AFEU, displayed in
data to be processed has been written to the input FIFO (in channel-driven access, this signaling is done
automatically). Before this register is written, the AFEU does not process the last block of data in its input
FIFO. Once the end of message register is written, the AESU processes any remaining data in the input
FIFO and generates the done interrupt. If the DC(dump context) bit in the AFEU mode register is set, the
context is written to the output FIFO following the last message word.
Any value written to the end of message register has the same effect. A read of the AFEU end of message
register always returns a zero value.
10.7.2.9
An ARC4 encryption session begins with an initial key permutation to generate the initial S-box state.
After that each subsequent message in the same session makes use of the S-box state and also modifies the
S-box state.
To implement this behavior using the AFEU, the first descriptor of a session must perform a key permute
operation. If there are additional messages in the same session, then at the end of each descriptor execution
the S-box state must be dumped out as context so that the next message of the session can re-load that
context.
AFEU context consists of two parts:
There is no standard data format for S-box state information. To ensure proper AFEU operation, the AFEU
context should only be written with data that was read from the AFEU context during a previous operation.
10.7.2.9.1
In the default mode of operation, the key and key size are provided to the AFEU. The initial memory values
in the S-box are permuted with the key to create new S-box values, which are used to encrypt the plaintext.
If the “prevent permute” (PP) mode bit is set in the AFEU mode register (see
Mode
10-96
Reset
Addr 0x3_8050
•
•
W
R
Register”), then the AFEU does not require a key, but instead requires context to set the S-box state
AFEU context memory — a 256-byte SRAM that holds the current S-box contents
AFEU context memory pointer register — holds the internal context pointers that are updated with
each byte of message processed. These pointers correspond to the values of I, J, and Sbox[I+1] in
the ARC4 algorithm.
0
AFEU End of Message Register
AFEU Context
Writing AFEU Context
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 10-39. AFEU End of Message Register
AFEU End of Message
All zeros
Figure
10-39, is used to signal the AFEU that all
Section 10.7.2.1, “AFEU
Freescale Semiconductor
Access: Write only
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