MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1071

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REQ is negated for at least one clock cycle. This prevents ill-behaved masters from monopolizing the bus.
When the broken master feature is disabled, a device that requests the bus and receives a grant never loses
its grant until and unless it begins a transaction or negates its REQ signal. Note that disabling the broken
master feature is not recommended.
16.4.1.4
In the sleep power-saving mode, the clock signal driving SYSCLK can be disabled. If the clock is disabled,
the arbitration logic is not able to perform its function. System programmers must park the bus with a
device that can sustain the PCI_AD[31:0], PCI_C/BE[3:0], and parity signals prior to disabling the
SYSCLK signal. If the bus is parked on the MPC8536E when its clocks are stopped, the MPC8536E
sustains the PCI_AD[31:0], PCI_C/BE[3:0], and parity signals in their prior states. In this situation, the
only way for another agent to use the PCI bus is by waking the MPC8536E. In nap and doze power-saving
modes, the arbiter continues to operate allowing other PCI devices to run transactions.
16.4.2
This section provides a general description of the PCI bus protocol. Specific PCI bus transactions are
described in
and
All signals are sampled on the rising edge of the PCI bus clock (SYSCLK). Each signal has a setup and
hold aperture with respect to the rising clock edge in which transitions are not allowed. Outside this
aperture, signal values or transitions have no significance. See the separate hardware specifications
document for specific setup and hold times.
16.4.2.1
The basic PCI bus transfer mechanism is a burst. A burst is composed of an address phase followed by one
or more data phases. Fundamentally, all PCI data transfers are controlled by three signals—PCI_FRAME
(frame), PCI_IRDY (initiator ready), and PCI_TRDY (target ready). An initiator asserts PCI_FRAME to
indicate the beginning of a PCI bus transaction and negates PCI_FRAME to indicate the end of a PCI bus
transaction. An initiator negates PCI_IRDY to force wait cycles. A target negates PCI_TRDY to force wait
cycles.
The PCI bus is considered idle when both PCI_FRAME and PCI_IRDY are negated. The first clock cycle
in which PCI_FRAME is asserted indicates the beginning of the address phase. The address and bus
command code are transferred in that first cycle. The next cycle begins the first of one or more data phases.
Data is transferred between initiator and target in each cycle that both PCI_IRDY and PCI_TRDY are
asserted. Wait cycles may be inserted in a data phase by the initiator (by negating PCI_IRDY) or by the
target (by negating PCI_TRDY).
Once an initiator has asserted PCI_IRDY, it cannot change PCI_IRDY or PCI_FRAME until the current
data phase completes regardless of the state of PCI_TRDY. Once a target has asserted PCI_TRDY or
PCI_STOP, it cannot change PCI_DEVSEL, PCI_TRDY, or PCI_STOP until the current data phase
completes. In simpler terms, once an initiator or target has committed to the data transfer, it cannot change
its mind.
Freescale Semiconductor
Figure 16-52
PCI Bus Protocol
Section 16.4.2.7, “PCI Bus Transactions.”
Power-Saving Modes and the PCI Arbiter
Basic Transfer Control
for examples of the transfer-control mechanisms described in this section.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Refer to
Figure
16-49,
Figure
16-50,
Figure
PCI Bus Interface
16-51,
16-45