MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1694

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

J–L
Interrupts
Index-8
overview, 9-1
performance monitor events, 24-21
processor core interrupt sources, 9-4
programming guidelines, 9-58
register descriptions, 9-19
reset of PIC, 9-21, 9-58
reset processor from software, 9-22, 9-58
signals summary, 9-8
simultaneous interrupts, priorities, 9-54
sources of interrupts, 9-5
spurious vector generation, 9-23, 9-55
vendor identification, 9-21
channel done, 10-35
channel error, 10-35
DDR, 8-57
DMA, 15-9–15-12, 15-14, 15-19, 15-23, 15-32
DUART
ECM interrupt register (ECM error enable
eTSEC, 14-171–14-174
general, 10-37
I
2
C interface
critical interrupt (cint) sources, 9-29
changing interrupt source configuration, 9-60
by acronym, see Register Index, 9-19
global registers, 9-19–9-23
global timer registers, 9-23–9-28
interrupt source configuration registers, 9-24–9-26,
message registers, 9-34–9-36
non-accessible registers
per-CPU registers, 9-46–9-51
performance monitor mask registers, 9-32–9-34
summary registers, 9-28–9-32
see also Signals, PIC
internal (to PIC) interrupt destinations, 9-29, 9-30, 9-31,
internal (to PIC) interrupt sources, 9-6
interrupt control logic, 12-23
interrupt enable and control registers, 12-7–12-10
interrupt registers, 14-27–14-33
calling address match condition, 11-6
flowchart for interrupt service routine, 11-24
interrupt after transfer, 11-22
interrupt enable bit (I2CCR[MIEN]), 11-8
interrupt on START, 11-22
interrupt pending status bit (I2CSR[MIF]), 11-10
interrupt-driven byte-to-byte transfers, 11-2
read of last byte, 11-22
interrupt pending register (IPR), 9-52
interrupt request register (IRR), 9-53
register—EEER), 7-7
9-40–9-46
9-32
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
IRQ[0:11] (interrupt request 0–11) signals, 9-8
IRQ[9:11] signal select
IRQ_OUT (interrupt request out) signal, 9-8, 9-28
Isochronous transfer descriptor (iTD), see USB interface,
J
JTAG test access port
L
L2 cache/SRAM
IRQ[9:11] signal select, 23-14
LBC interrupt register, 13-29
PCI/PCI-X error enable register, 16-26
performance monitor (PIC), 24-21
see also Interrupt controller (PIC)
split transaction, 21-86
global utilities, 23-14
signals summary, 25-5
allocation of lines, 6-32
block diagram, 6-1
coherency rules, 6-28
error handling registers, 6-17
error injection, 6-18
external writes, see stashing
flash clearing, instruction and data locks, 6-31
locking
memory map/register definition, 6-8
memory-mapped SRAM
memory-mapped windows, 2-4
operation, 6-33
overview, 6-1
performance monitor events, 24-26
PLRU bit update considerations, 6-32
register descriptions, 6-10–6-25
replacement policy, 6-31
SRAM features, 6-2
stashing, 6-25
state transitions, 6-35
slave mode interrupt service routine guidelines, 11-23
isochronous (high-speed) transfer descriptor (iTD)
see also Signals, JTAG, 25-5
clearing locks on selected lines, 6-30
entire, 6-29
programmed memory ranges, 6-30
selected lines, 6-30
with stale data, 6-31
coherency rules, 6-29
due to core-initiated transactions, 6-35
due to system-initiated transactions, 6-38
for slave transmitter routine, 11-23
loss of arbitration, 11-24
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Index