MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1102

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17.3.1
The PCI Express memory mapped registers are accessed by reading and writing to an address comprised
of the base address (specified in the CCSRBAR on the local side or the PEXCSRBAR on the PCI Express
side) plus the block base address, plus the offset of the specific register to be accessed. Note that all
memory-mapped registers (except the PCI Express configuration data register, PEX_CONFIG_DATA)
must only be accessed as 32-bit quantities.
Also note that although the table explicitly lists only the registers for the PCI Express controller 1, the
register map for PCI Express controllers 2 and 3 are the same except for the block base address.
Memory-mapped registers for PCI Express controller 1 begin at block base address 0x0_A000, controller
2 registers begin at 0x0_9000, and controller 3 registers begin at 0x0_B000.
Table 17-3
descriptions, the following access definitions apply:
17-6
0x018–
Offset
0x00C
0x01C
0x000
0x004
0x008
0x010
0x014
0x020
0x024
•
•
•
•
•
Reserved fields are always ignored for the purposes of determining access type.
R/W, R, and W (read/write, read only, and write only) indicate that all the non-reserved fields in a
register have the same access type.
w1c indicates that all of the non-reserved fields in a register are cleared by writing ones to them.
Mixed indicates a combination of access types.
Special is used when no other category applies. In this case the register figure and field description
table should be read carefully.
PEX_CONFIG_ADDR—PCI Express configuration address register
PEX_CONFIG_DATA—PCI Express configuration data register
Reserved
PEX_OTB_CPL_TOR—PCI Express outbound completion timeout
register
PEX_CONF_RTY_TOR—PCI Express configuration retry timeout
register
PEX_CONFIG—PCI Express configuration register
Reserved
PEX_PME_MES_DR—PCI Express PME & message detect register
PEX_PME_MES_DISR—PCI Express PME & message disable
register
lists the memory-mapped registers. In this table and in the register figures and field
PCI Express Memory Mapped Registers
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 17-3. PCI Express Memory-Mapped Register Map
PCI Express Power Management Event & Message Registers
PCI Express Controller 1 —Block Base Address 0x0_A000
PCI Express Controller 3—Block Base Address 0x0_B000
PCI Express Controller 2—Block Base Address 0x0_9000
PCI Express Controller 1 Memory-Mapped Registers
PCI Express Configuration Access Registers
Register
Access
R/W
R/W
R/W
R/W
R/W
R/W
w1c
—
—
0x0010_FFFF
0x0400_FFFF
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
—
—
Freescale Semiconductor
17.3.2.1/17-10
17.3.2.2/17-10
17.3.2.3/17-11
17.3.2.4/17-12
17.3.2.5/17-12
17.3.3.1/17-13
17.3.3.2/17-15
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