MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1107

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

are allowed. Also note that accesses to the little-endian PCI Express configuration space must be properly
formatted. See
The fields of the PCI Express configuration data register are described in
17.3.2.3
The PCI Express outbound completion timeout register, shown in
time for a response to come back as a result of an outbound non-posted request before a timeout condition
occurs.
The fields of the PCI Express outbound completion timeout register are described in
Freescale Semiconductor
Offset 0x00C
Reset 0
8–31
Bits
1–7
0–31
Bits
0
Offset 0x004
Reset
W
R
W
TD
R
0
Name
Data
Name
Figure 17-4. PCI Express Outbound Completion Timeout Register (PEX_OTB_CPL_TOR)
0
TD
TC
—
0
1
0
PCI Express Outbound Completion Timeout Register
(PEX_OTB_CPL_TOR)
Section 17.4.1.2.1, “Byte Order for Configuration
Figure 17-3. PCI Express Configuration Data Register (PEX_CONFIG_DATA)
A read or write to this register starts a PCI Express configuration cycle if the PEX_CONFIG_ADDR enable
bit is set (PEX_CONFIG_ADDR[EN] = 1).
Timeout disable. This bit controls the enabling/disabling of the timeout function.
0 Enable completion timeout
1 Disable completion timeout
Reserved
Timeout counter. This is the value that is used to load the response counter of the completion timeout.
One TC unit is 8× the PCI Express controller clock period; that is, one TC unit is 20 ns at 400 MHz, and 30
ns at 266.66 MHz.
The following are examples of timeout periods based on different TC settings:
0x00_0000
0x10_FFFF 22.28 ms at 400 MHz controller clock; 33.34 ms at 266.66 MHz controller clock
0xFF_FFFF335.54 ms at 400 MHz controller clock; 503.31 ms at 266.66 MHz controller clock
0
—
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
5
0
Reserved
Table 17-6. PEX_OTB_CPL_TOR Field Descriptions
Table 17-5. PEX_CONFIG_DATA Field Descriptions
0
7
0
8
0
0
1
0
0
0
All zeros
0
Data
Description
Description
1
1
1
Figure
Transactions,” for more information.
1
TC
1
17-4, contains the maximum wait
1
Table
1
1
PCI Express Interface Controller
17-5.
1
1
Table
1
Access: Read/Write
Access: Read/Write
1
17-6.
1
1
1
17-11
31
1
31