MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1651

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
0x13D0–
0x1200–
0x1440–
0x11B0
0x11C0
0x11D0
0x11E0
0x13A0
0x13A4
0x13B0
0x13C0
0x13C4
0x11F0
0x12F0
0x13F0
0x14F0
0x1300
0x1308
0x1310
0x1320
0x1324
0x1330
0x1340
0x1344
0x1350
0x1360
0x1364
0x1370
0x1380
0x1384
0x1390
0x1400
0x1410
0x1420
0x1430
0x1500
0x1510
Offset
GTDRA2—Global timer 2 destination register (Group A)
GTCCRA3—Global timer 3 current count register (Group A)
GTBCRA3—Global timer 3 base count register (Group A)
GTVPRA3—Global timer 3 vector/priority register (Group A)
GTDRA3—Global timer 3 destination register (Group A)
Reserved
TCRA—Timer control register (Group A)
ERQSR—External interrupt summary register
IRQSR0—IRQ_OUT summary register 0
IRQSR1—IRQ_OUT summary register 1
IRQSR2—IRQ_OUT summary register 2
CISR0—Critical interrupt summary register 0
CISR1—Critical interrupt summary register 1
CISR2—Critical interrupt summary register 2
PM0MR0—Performance monitor 0 mask register 0
PM0MR1—Performance monitor 0 mask register 1
PM0MR2—Performance monitor 0 mask register 2
PM1MR0—Performance monitor 1 mask register 0
PM1MR1—Performance monitor 1 mask register 1
PM1MR2—Performance monitor 1 mask register 2
PM2MR0—Performance monitor 2 mask register 0
PM2MR1—Performance monitor 2 mask register 1
PM2MR2—Performance monitor 2 mask register 2
PM3MR0—Performance monitor 3 mask register 0
PM3MR1—Performance monitor 3 mask register 1
PM3MR2—Performance monitor 3 mask register 2
Reserved
MSGR0—Message register 0
MSGR1—Message register 1
MSGR2—Message register 2
MSGR3—Message register 3
Reserved
MER—Message enable register
MSR—Message status register
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
PIC Global Registers—Block Base Address 0x4_0000
Table A-14. PIC Global Registers (continued)
Register
Complete List of Configuration, Control, and Status Registers
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
—
—
R
R
R
R
R
R
R
R
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0xFFFF_FFFF
0x0000_0001
0x0000_0000
0x8000_0000
0x8000_0000
0x0000_0001
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
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9.3.2.2/9-24
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9.3.2.6/9-27
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A-39