MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 425

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.4.1.2.3
Under certain circumstances, the PIC has no valid vector to return to a processor core during an interrupt
acknowledge cycle. In these cases, the spurious vector from the spurious vector register is returned. The
following cases cause a spurious vector fetch:
In all cases, a spurious vector is returned only if no pending interrupt has sufficient priority to signal an
interrupt, otherwise, the vector for that interrupt source is returned.
9.4.1.2.4
While an interrupt is being handled, if an interrupt request arrives with a higher xVPRn[PRIORITY] value,
the interrupt being serviced is superseded. As described in
PIC asserts int, and the newer, higher priority interrupt is handled. This happens even if software, as part
of its interrupt service routine, updates the corresponding CTPR with a lower value.
Thus, although several interrupts can be in service simultaneously (and tracked by the ISR), the highest
priority interrupt by that processor is always the one actively handled. When the interrupt routine
completes, it performs a write EOI cycle, a side effect of which is to take the current highest priority
interrupt out of service (removes it from the ISR). At this point, the interrupt selector chooses the new
highest priority interrupt request, and, assuming CTPR[TASKP] has not been updated to a value higher
than the new interrupt, the PIC asserts int on its behalf.
The next write EOI cycle takes the current highest priority interrupt out of service. An interrupt with lower
priority than those in service is not started until all higher priority interrupts complete even if its priority
is greater than the CTPR value.
9.4.2
Processors 0 and 1 can generate interprocessor interrupts that target either or both processors. A self
interrupt occurs when a core dispatches an interprocessor interrupt event to itself. Interrupts are initiated
by writing either or both of the POn bits in an interprocessor interrupt dispatch register (IPIDR0–IPIDR3)
of one of the four IPI channels. If subsequent interprocessor interrupts from a given channel to a given
target processor are initiated before the first is acknowledged, only one interrupt is generated.
Freescale Semiconductor
•
•
•
•
int is asserted in response to an externally or internally-sourced interrupt which is activated with
level-sensitive logic, and the asserted level is negated before the interrupt is acknowledged.
int is asserted for an interrupt source that is later masked (using the mask bit in the vector/priority
register corresponding to that source) before the interrupt is acknowledged.
int is asserted for an interrupt source that is later masked by an increase in the task priority level
before the interrupt is acknowledged.
An interrupt acknowledge cycle is performed by the processor core in spite of the fact that the int
signal has not been asserted by the PIC.
Interprocessor Interrupts
Spurious Vector Generation
EOI should not be written in response to a spurious vector. Otherwise, a
previously accepted interrupt might be cleared unintentionally.
Nesting of Interrupts
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
NOTE
Section 9.4.1.2, “Interrupts Routed to int,”
Programmable Interrupt Controller (PIC)
9-55
the