MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1284

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Secure Digital Host Controller
Table 20-7
Table 20-8
command CRC check enable, and response type bits.
20-10
DMAEN
BCEN
Field
30
31
Multi/Single Block Select
XFERTYP[MSBSEL]
shows how register settings determine types of data transfers.
shows how the response type can be determined by the command index check enable,
XFERTYP[RSPTYP]
Block count enable. Enables the block attributes register, which is only relevant for multiple block transfers.
When this bit is cleared, the block attributes register is disabled, which is useful in executing an infinite transfer.
0 Disable
1 Enable
DMA enable. Enables DMA functionality as described in
a DMA operation should begin when the host driver writes to the CMDINX field of the transfer type register.
0 Disable
1 Enable
Response Type
The CRC field for R3 and R4 is expected to be all 1s. The CRC check should
be disabled for these response types.
Table 20-8. Relation Between Parameters and Name of Response Type
0
1
1
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
00
01
10
10
11
Table 20-6. XFERTYP Field Descriptions (continued)
Table 20-7. Determination of Transfer Type
Index Check Enable
Block Count Enable
XFERTYP[CICEN]
XFERTYP[BCEN]
Don’t Care
0
0
0
1
1
0
1
1
NOTE
Description
BLKATTR[BLKCNT]
CRC Check Enable
XFERTYP[CCCEN]
Positive Number
Block Count
Don’t Care
Don’t Care
Section 20.5.2, “DMA CCB Interface.”
Zero
0
1
0
1
1
Response Type
No Response
No Data Transfer
Multiple Transfer
Infinite Transfer
Single Transfer
R1, R5, R6
R1b, R5b
R3, R4
Function
R2
Freescale Semiconductor
If this bit is set,