MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1578

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Number of rejected frames due to filer
error
Number of cycles Rx FIFO > 1/4 full
Number of cycles Rx FIFO > 1/2 full
Number of cycles Rx FIFO > 3/4 full
Number of cycles Rx FIFO = full
Number of accepted frames matc
Number of accepted frams to station
address
Number of accepted unicaset frames via
has
Number of accepted group frames via
hash
Number of accepted frams via exact
match
Number of rejected frames at layer 2
Number of RX interrupts signalled
Number of TX interrupts signalled
RX data write lifetime (Duration Thresh-
old)
Number of RX packets received while
RX FIFO is full
Inbound G2PI read
Inbound G2PI write
Inbound G2PI data
Outbound G2PI read
Outbound G2PI write
Outbound G2PI data
Device Performance Monitor
24-24
Event Counted
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 24-10. Performance Monitor Events (continued)
Number
C3:116
C1:109
C2:116
C3:118
C8:102
C7:100
C4:111
C2:112
C8:119
C9:101
C5:124
C6:126
C7:125
C8:124
Ref:45
Ref:49
C9:97
C9:91
C6:90
C5:95
C3:85
PCI Express 1 Events
Number of rejected frames due to filer error
Number of cycles Rx FIFO > 1/4 full
Number of cycles Rx FIFO > 1/2 full
Number of cycles Rx FIFO > 3/4 full
Number of cycles Rx FIFO = full
—
—
—
—
—
—
—
—
—
—
A single pulse to indicate an inbound PCI Express 1 read has
occurred.
A single pulse to indicate an inbound PCI Express 1 write has
occurred.
A level signal to indicate the amount of data transferred if any for
inbound PCI Express 1 request. Active for every beat of
PCI Express 1 data.
A single pulse to indicate an outbound PCI Express 1 read has
occurred.
A single pulse to indicate an outbound PCI Express 1 write has
occurred.
A level signal to indicate the amount of data transferred if any for
outbound PCI Express 1 request. Active for every beat of
PCI Express 1 data.
Description of Event Counted
Freescale Semiconductor