MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 741

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.5.5
Connecting the local bus UPM controller to a DRAM device requires a detailed examination of the timing
diagrams representing the possible memory cycles that must be performed when accessing this device.
This section describes timing diagrams for various UPM configurations for fast-page mode DRAM, with
LCRR[CLKDIV] = 4 (clock ratio of 8) or 8 (clock ratio of 16). These illustrative examples may not
represent the timing necessary for any specific device used with the eLBC. Here, LGPL1 is programmed
to drive R/W of the DRAM, although any LGPLn signal may be used for this purpose.
Freescale Semiconductor
Register
Interfacing to Fast-Page Mode DRAM Using UPM
FBAR
FBCR
FPAR
MDR
FCR
FIR
Table 13-49. FCM Register Settings for Page Program (OR n [PGS] = 1)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
(e.g. block 0x00010AB4)
locates page 5, buffer 1)
(e.g. 0x00005000
Initial Contents
0x41286DB0
0x80701000
0x00000000
block index
page offset
—
CMD0 = 0x80 = page address and data entry;
CMD1 = 0x70 = read status
CMD2 = 0x10 = program page;
BLK locates index of 128-Kbyte block
PI locates page index in BLK;
PI mod 2 indexes FCM buffer RAM;
MS = 0 and CI = 0
BC = 0 to write entire 2112-Byte page with ECC generation
returns with AS0 holding program status
OP0 = CM0 = command 0;
OP1 = CA = column address;
OP2 = PA = page address;
OP3 = WB = write data from buffer;
OP4 = CM2 = command 2;
OP5 = CW1 = wait on Flash ready and issue command 1;
OP6 = RS = read erase status into MDR[AS0];
OP7 = NOP
Description
Enhanced Local Bus Controller
13-99