MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 283

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
MODT[0:3]
MDIC[0:1]
MDM[0:8]
MAPAR_
MAPAR_
Signal
ERR
OUT
Table 8-3. Memory Interface Signals—Detailed Signal Descriptions (continued)
I/O
I/O Driver impedance calibration. Note that the MDIC signals require the use of 18.2-
O
O
O
I
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
DDR SDRAM data output mask. Masks unwanted bytes of data transferred during a write. They are
needed to support sub-burst-size transactions (such as single-byte writes) on SDRAM where all I/O
occurs in multi-byte bursts. MDM0 corresponds to the most significant byte (MSB) and MDM7
corresponds to the LSB, while MDM8 corresponds to the ECC byte.
encodings.
On-Die termination. Memory controller outputs for the ODT to the DRAM. MODT[0:3] represents the
on-die termination for the associated data, data masks, ECC, and data strobes.
resistors; MDIC0 must be pulled to GND, while MDIC1 must be pulled to GV
Control Driver Register 2
Address parity error. Reflects whether an address parity error has been detected by the DRAM. This
signal is active low.
Address parity out. Driven by the memory controller as the parity bit calculated across the address and
command bits. Even parity is used, and parity is not calculated for the MCKE[0:3], MODT[0:3], or
MCS[0:3] signals.
Meaning
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—Same timing as MDQx as outputs.
Timing Assertion/Negation—Driven in accordance with JEDEC DRAM specifications for on-die
Timing These are driven for four DRAM cycles at a time while the DDR controller is executing the
Timing Assertion/Negation—are driven by the registered DIMMs one DRAM cycle after the parity bit
Timing Assertion/Negation—are issued one DRAM cycle after the chip select for each command.
State
State
State
State
State
Asserted—Prevents writing to DDR SDRAM. Asserted when data is written to DRAM if the
Negated—Allows the corresponding byte to be read from or written to the SDRAM.
High impedance—Always driven unless the memory controller is disabled.
Asserted/Negated—Represents the ODT driven by the DDR memory controller.
High impedance—Always driven.
These pins are used for automatic calibration of the DDR IOs.
Asserted—An error has been detected.
Negated—An error has not been detected.
Asserted—The parity bit is high.
Negated—The parity bit is low.
corresponding byte(s) should be masked for the write. Note that the MDM n signals are
active-high for the DDR controller. MDM n is part of the DDR command encoding.
termination timings. It is configured through the CS n _CONFIG[ODT_RD_CFG] and
CS n _CONFIG[ODT_WR_CFG] fields.
automatic driver compensation.
has been driven by the memory controller. This error signal should be held valid for two
DRAM cycles.
(DDRCDR_2),” for more information on these signals.
Description
Table 8-50
DD
.
Section 8.4.1.28, “DDR
shows byte lane
DDR Memory Controller
precision 1%
8-9