MPC8536E-ANDROID Freescale Semiconductor, MPC8536E-ANDROID Datasheet - Page 1690

• Manufacturer Part Number: MPC8536E-ANDROID
• Description: HARDWARE/SOFTWARE ANDROID OS
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC ™r
• Type: MPUr

Specifications of MPC8536E-ANDROID

• Contents: Board
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

E–E
E
e500 coherency module (ECM)
Index-4
baud-rate generator logic, 12-20
block diagram, 12-2
divisor latch access bit (ULCRn[DLAB]), 12-3, 12-11
error handling, 12-21
errors detected, 12-2
features, 12-1
functional description, 12-19
initialization/application information, 12-23
interrupts
memory map/register definition, 12-3
modes of operation, 12-2
overview, 12-1
PC16450 UART compatibility, 12-1
performance monitor events, 24-26
register descriptions, 12-5–12-19
serial interface data format, 12-2
serial interface operation, 12-19–12-20
signals summary, 12-3
block diagram, 7-1
CCB arbiter, 7-9
CCB interface, 7-10
configuration
error handling
features, 7-2
functional description, 7-9
global data multiplexor, 7-10
I/O arbiter, 7-9
parity bit, 12-20
START bit, 12-20
STOP bit, 12-20
framing error, 12-8, 12-15, 12-20, 12-21
overrun error, 12-22
parity error, 12-22
interrupt control logic, 12-23
interrupt enable and control registers, 12-7–12-10
DMA mode selection, 12-22
FIFO mode, 12-22
local loopback mode, 12-21
UART0 register offsets, 12-3
UART1 register offsets, 12-3
data transfer, 12-20
START bit, 12-20
STOP bit, 12-20
transaction protocol example, 12-19
see also Signals, DUART
CCB address configuration register (EEBACR), 7-3
CCB port configuration register (EEBPCR), 7-4
error handling registers, 7-6–7-9
interrupts, 12-22
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
e500 core
EC_GTX_CLK125 (eTSEC gigabit transmit 125 MHz
EC_MDC (eTSEC management data clock) signal, 14-11
EC_MDIO (eTSEC management data input/output, BIDI)
Error handling
eTSEC
initialization/application information, 7-10–7-11
interrupts
memory map/register definition, 7-3
overview, 7-2
performance monitor events, 24-19
register descriptions, 7-3
transaction queue, 7-10
boot mode (POR), 4-17
interrupts
registers
time base
DDR, 8-53–8-60, 8-86
DMA, 15-32
DUART, 12-2, 12-21
ECM
eTSEC, 14-175–14-176
I
L2 cache/SRAM
LBC
PCI Express registers, 17-30–17-43
PCI/PCI-X
block diagram, 14-2
2
C interface
ECM error enable register (EEER), 7-7
by acronym, see Register Index
sources, 9-4
PVR (processor version register), 5-6
SVR (system version register), 23-30
TCR (timer control register), 5-5
RTC (real time clock) signal options, 4-3, 4-26
source) signal, 14-11
signal, 14-11
framing error, 12-8, 12-15, 12-20, 12-21
overrun error, 12-22
parity error, 12-22
error handling registers, 7-6–7-9
boot sequencer mode, 11-19
error handling registers, 6-17
error injection, 6-18
transfer error registers, 13-26–13-31
address/data parity, 16-54, 16-65, 16-66
reporting, 16-65–16-66
retry transactions, 16-53
target-abort, 16-53
target-disconnect, 16-53
PERR and SERR signals, 16-66
target-initiated termination, 16-53
Freescale Semiconductor
Index