ST72C334J4T6 STMicroelectronics, ST72C334J4T6 Datasheet - Page 106

• Manufacturer Part Number: ST72C334J4T6
• Description: MCU 8BIT FLASH SPI SCI 44TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72C334J4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3.2 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72C3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 3.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7C334-INDART, ST7MDT2-EPB2/US
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4838

ST72334J/N, ST72314J/N, ST72124J
INSTRUCTION GROUPS (Cont’d)
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JRULE
LD
MUL
NEG
NOP
OR
POP
PUSH
RCF
RET
RIM
RLC
RRC
RSP
SBC
SCF
SIM
SLA
SLL
SRL
SRA
SUB
SWAP
TNZ
TRAP
WFI
XOR
Mnemo
Jump if (C + Z = 1)
Load
Multiply
Negate (2's compl)
No Operation
OR operation
Pop from the Stack
Push onto the Stack
Reset carry flag
Subroutine Return
Enable Interrupts
Rotate left true C
Rotate right true C
Reset Stack Pointer
Subtract with Carry
Set carry flag
Disable Interrupts
Shift left Arithmetic
Shift left Logic
Shift right Logic
Shift right Arithmetic
Subtraction
SWAP nibbles
Test for Neg & Zero
S/W trap
Wait for Interrupt
Exclusive OR
Description
Unsigned <=
dst <= src
X,A = X * A
neg $10
A = A + M
pop reg
pop CC
push Y
C = 0
I = 0
C <= Dst <= C
C => Dst => C
S = Max allowed
A = A - M - C
C = 1
I = 1
C <= Dst <= 0
C <= Dst <= 0
0 => Dst => C
Dst7 => Dst => C
A = A - M
Dst[7..4] <=> Dst[3..0] reg, M
tnz lbl1
S/W interrupt
A = A XOR M
Function/Example
reg, M
A, X, Y
reg, M
A
reg
CC
M
reg, M
reg, M
A
reg, M
reg, M
reg, M
reg, M
A
A
Dst
M, reg
X, Y, A
M
M
M
reg, CC
M
M
M
Src
H
H
0
0
1
1
0
I
I
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
0
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C
C
C
C
C
C
C
C
C
0
0
1