ST72C334J4T6 STMicroelectronics, ST72C334J4T6 Datasheet - Page 88

• Manufacturer Part Number: ST72C334J4T6
• Description: MCU 8BIT FLASH SPI SCI 44TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72C334J4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3.2 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72C3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 3.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7C334-INDART, ST7MDT2-EPB2/US
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4838

ST72334J/N, ST72314J/N, ST72124J
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
14.5.5.2 Transmitter
The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the CR1 reg-
ister.
Character Transmission
During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the DR register consists of a buffer (TDR) between
the internal bus and the transmit shift register (see
Figure 1.).
Procedure
– Select the M bit to define the word length.
– Select the desired baud rate using the BRR and
– Set the TE bit to assign the TDO pin to the alter-
– Access the SR register and write the data to
Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SR register
2. A write to the DR register
The TDRE bit is set by hardware and it indicates:
– The TDR register is empty.
– The data transfer is beginning.
– The next data can be written in the DR register
This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.
When a transmission is taking place, a write in-
struction to the DR register stores the data in the
TDR register and which is copied in the shift regis-
ter at the end of the current transmission.
When no transmission is taking place, a write in-
struction to the DR register places the data directly
in the shift register, the data transmission starts,
and the TDRE bit is immediately set.
88/153
the ETPR registers.
nate function and to send a idle frame as first
transmission.
send in the DR register (this sequence clears the
TDRE bit). Repeat this sequence for each data to
be transmitted.
without overwriting the previous data.
When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
and an interrupt is generated if the TCIE is set and
the I bit is cleared in the CCR register.
Clearing the TC bit is performed by the following
software sequence:
1. An access to the SR register
2. A write to the DR register
Note: The TDRE and TC bits are cleared by the
same software sequence.
Break Characters
Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see Figure 2.).
As long as the SBK bit is set, the SCI send break
frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.
Idle Characters
Setting the TE bit drives the SCI to send an idle
frame before the first data frame.
Clearing and then setting the TE bit during a trans-
mission sends an idle frame after the current word.
Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set i.e. before writing the next byte in the DR.