ST72C334J4T6 STMicroelectronics, ST72C334J4T6 Datasheet - Page 29

• Manufacturer Part Number: ST72C334J4T6
• Description: MCU 8BIT FLASH SPI SCI 44TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72C334J4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3.2 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72C3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 3.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7C334-INDART, ST7MDT2-EPB2/US
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4838

RESET SEQUENCE MANAGER (Cont’d)
9.2.2 Asynchronous External RESET pin
The RESET pin is both an input and an open-drain
output with integrated R
This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.
A RESET signal originating from an external
source must have a duration of at least t
order to be recognized. This detection is asynchro-
nous and therefore the MCU can enter reset state
even in HALT mode.
The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.
Two RESET sequences can be associated with
this RESET source: short or long external reset
pulse (see
Starting from the external RESET pulse recogni-
tion, the device RESET pin acts as an output that
is pulled low during at least t
Figure 16. RESET Sequences
WATCHDOG
RESET
EXTERNAL
RESET
SOURCE
RESET PIN
V
V
IT+
IT-
Figure
RUN
V
DD
16).
ON
DELAY
RESET
weak pull-up resistor.
LVD
w(RSTL)out
.
t
t
h(RSTL)in
w(RSTL)out
h(RSTL)in
RUN
in
DELAY
SHORT EXT.
RESET
9.2.3 Internal Low Voltage Detection RESET
Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:
The device RESET pin acts as an output that is
V
The LVD filters spikes on V
avoid parasitic resets.
9.2.4 Internal Watchdog RESET
The RESET sequence generated by a internal
Watchdog counter overflow is shown in
low during at least t
pulled low when V
Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
DD
t
Power-On RESET
Voltage Drop RESET
h(RSTL)in
<V
RUN
ST72334J/N, ST72314J/N, ST72124J
IT-
(falling edge) as shown in
WATCHDOG UNDERFLOW
DELAY
LONG EXT.
RESET
w(RSTL)out
DD
<V
RUN
DD
IT+
INTERNAL RESET (4096 T
FETCH VECTOR
.
larger than t
DELAY
(rising edge) or
WATCHDOG
RESET
t
w(RSTL)out
Figure
Figure
g(VDD)
16.
RUN
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CPU
16.
to
)