ST72C334J4T6 STMicroelectronics, ST72C334J4T6 Datasheet - Page 41

• Manufacturer Part Number: ST72C334J4T6
• Description: MCU 8BIT FLASH SPI SCI 44TQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72C334J4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3.2 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Processor Series: ST72C3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 4 bit
• Operating Supply Voltage: 3.2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7C334-INDART, ST7MDT2-EPB2/US
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-4838

I/O PORTS (Cont’d)
Table 7. I/O Port Configurations
Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,
2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,
reading the DR register will read the alternate function output status.
the alternate function reads the pin status given by the DR register content.
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS
PAD
PAD
PAD
V
V
V
DD
R
DD
DD
R
R
PU
PU
PU
PULL-UP
CONFIGURATION
Hardware Configuration
INTERRUPT
CONFIGURATION
OTHER
FROM
PINS
ST72334J/N, ST72314J/N, ST72124J
ALTERNATE
ALTERNATE
REGISTER
ENABLE
ENABLE
DR
DR REGISTER ACCESS
REGISTER
REGISTER
SELECTION
POLARITY
DR
DR
DR REGISTER ACCESS
DR REGISTER ACCESS
W
R
ALTERNATE
ALTERNATE
OUTPUT
OUTPUT
ALTERNATE INPUT
EXTERNAL INTERRUPT
SOURCE (ei
ANALOG INPUT
R/W
R/W
DATA BUS
DATA BUS
DATA BUS
x
)
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