TMP86FH46ANG(Z) Toshiba, TMP86FH46ANG(Z) Datasheet
TMP86FH46ANG(Z)
Specifications of TMP86FH46ANG(Z)
Related parts for TMP86FH46ANG(Z)
TMP86FH46ANG(Z) Summary of contents
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Bit Microcontroller TLCS-870/C Series TMP86FH46ANG ...
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... Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations ...
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Difference among product (TMP86xx46 Series) 86CH46 86C846 86CH46A 8192bytes 16384bytes ROM (MASK) (MASK) RAM 512bytes 512bytes DBR(note1) I/O Large current output Interrupt Timer counter UART SIO Key-on wakeup 10-bit AD converter VDD Structure R of TEST pin R IN Terminal ...
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Difference among product (TMP86xx47 Series) 86CH47 86C847 86CH47A 8192bytes 16384bytes ROM (MASK) (MASK) RAM 512bytes 512bytes DBR(note1) I/O Large current output Interrupt Timer counter UART SIO Key-on wakeup 10-bit AD converter Structure R of TEST pin R IN Terminal for ...
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Differences in Electrical Characteristics (TMP86xx46 Series) 86C846 / 86CH46 / 86CM46 86CM46A 86PM46 [V] 5.5 4.5 Read/ 2.7 Fetch 1 [MHz] Operat- (a) 1.8V to 5.5V (- ℃ ) ing con- dition (MCU mode) ...
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Differences in Electrical Characteristics (TMP86xx47 Series) 86C847 / 86CH47 / 86CM47 86CM47A 86PM47 [V] 5.5 4.5 Read/ 2.7 Fetch 1 [MHz] Operat- (a) 1.8V to 5.5V (- ℃ ) ing con- dition (MCU mode) ...
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Date Revision 2006/2/23 1 2006/3/13 2 2006/6/29 3 2006/10/8 4 Revision History First Release Contents Revised Periodical updating.No change in contents. Contents Revised ...
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...
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Table of Contents Difference among product (TMP86xx46 Series) TMP86FH46ANG 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Using data transfer instructions 3.4.3 Interrupt return ........................................................................................................................................ 40 3.5 Software Interrupt (INTSW ...
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TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Package Dimension This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI). vi ...
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... The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by impli- cation or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C • ...
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Features Pulse width modulation (PWM) output, Programmable pulse generation (PPG) modes 8. High-Speed SIO: 1ch 9. 8-bit UART : 1 ch 10. 10-bit successive approximation type AD converter - Analog input 11. Key-on wakeup : 4 ch ...
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Pin Assignment (STOP2/AIN4) P34 (STOP3/AIN5) P35 (STOP4/AIN6) P36 (STOP5/AIN7) P37 P32 (AIN2) (AIN3) P33 1 42 P31 (AIN1 P30 (AIN0 P10 ( PDO3/PWM3 4 39 P11 (INT1 VAREF P12 (INT2/TC1 AVDD ...
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Block Diagram 1.3 Block Diagram Figure 1-2 Block Diagram Page 4 TMP86FH46ANG ...
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Pin Names and Functions The TMP86FH46ANG has MCU mode, parallel PROM mode, and serial PROM mode. Table 1-1 shows the pin functions in MCU mode. The serial PROM mode is explained later in a separate chapter. Table 1-1 Pin ...
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Pin Names and Functions Table 1-1 Pin Names and Functions(2/2) Pin Name P36 AIN6 STOP4 P35 AIN5 STOP3 P34 AIN4 STOP2 P33 AIN3 P32 AIN2 P31 AIN1 P30 AIN0 P47 P46 P45 P44 P43 P42 P41 P40 XIN XOUT ...
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Operational Description 2.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, and the reset ...
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System Clock Controller The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Example :Clears RAM to “00H”. (TMP86FH46ANG) SRAMCLR: 2.2 System Clock Controller The ...
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High-frequency clock XIN XOUT XIN (a) Crystal/Ceramic (b) External oscillator resonator Figure 2-3 Examples of Resonator Connection Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with dis- abling all interrupts and watchdog ...
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System Clock Controller 2.2.2 Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1. Generation of ...
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Timing Generator Control Register TBTCR (0036H) (DVOEN) (DVOCK) Selection of input to the 7th stage DV7CK of the divider Note 1: In single clock mode, do not set DV7CK to “1”. Note 2: Do not set “1” ...
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System Clock Controller (2) IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2<IDLE> ...
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Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2<XEN>. In SLOW1 and SLEEP modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. ...
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System Clock Controller IDLE1 mode (a) Single-clock mode IDLE2 mode SLEEP2 mode SLEEP1 mode (b) Dual-clock mode Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1 and IDLE2 are called ...
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System Control Register 1 SYSCR1 (0038H) STOP RELM RETM OUTEN STOP STOP mode start Release method for STOP RELM mode Operating mode after STOP RETM mode OUTEN Port output during STOP mode Warm-up time at releasing WUT ...
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System Clock Controller Note 8: Before setting TGHALT to “1”, be sure to stop peripherals. If peripherals are not stopped, the interrupt latch of peripherals may be set after IDLE0 or SLEEP0 mode is released. 2.2.4 Operating Mode Control ...
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Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST (P2PRD). 0 JRS F, SINT5 LD (SYSCR1), 01010000B DI SET (SYSCR1). 7 SINT5: RETI STOP pin XOUT pin NORMAL operation Confirm by program that the STOP ...
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System Clock Controller STOP mode is released by the following sequence the dual-clock mode, when returning to NORMAL2, both the high-frequency and low warm-up period is inserted to allow oscillation time to stabilize. During warm ...
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Figure 2-9 STOP Mode Start/Release Page 19 TMP86FH46ANG ...
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System Clock Controller 2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and ...
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Start the IDLE1/2 and SLEEP1/2 modes After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2 and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2<IDLE> to “1”. • Release the IDLE1/2 ...
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System Clock Controller Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Page 22 TMP86FH46ANG ...
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IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1. Timing ...
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System Clock Controller • Start the IDLE0 and SLEEP0 modes • Release the IDLE0 and SLEEP0 modes of TBT and TBTCR<TBTEN>. cleared to “0” and the operation mode is returned to the mode preceding IDLE0 and SLEEP0 modes. Before ...
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Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Page 25 TMP86FH46ANG ...
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System Clock Controller 2.2.4.4 SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter. (1) Switching from NORMAL2 mode to SLOW1 mode First, ...
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Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2<XEN> to turn on the high-frequency oscillation. When time for stabilization (Warm up) has been taken by the timer/counter (TC4,TC3), clear SYSCR2<SYSCK> to switch the main system clock to the ...
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System Clock Controller Figure 2-14 Switching between the NORMAL2 and SLOW Modes Page 28 TMP86FH46ANG ...
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Reset Circuit The TMP86FH46ANG has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and ...
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Reset Circuit 2.3.2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1<ATAS> is set to “1”), DBR or ...
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Reset Circuit Page 32 TMP86FH46ANG ...
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Interrupt Control Circuit The TMP86FH46ANG has a total of 18 interrupt sources excluding reset, of which 2 source levels are multi- plexed. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest ...
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Interrupt enable register (EIR) Since interrupt latches can be read, the status for interrupt requests can be monitored by software. Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to ...
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Example 1 :Enables interrupts individually and sets IMF DI LDW : : EI Example 2 :C compiler description example unsigned int _io (3AH) EIRL; _DI(); EIRL = 10100000B; : _EI(); ← ; IMF 0 (EIRL), 1110100010100000B ; EF15 to EF13, ...
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Interrupt enable register (EIR) Interrupt Latches 15 14 ILH,ILL (003DH, 003CH) IL15 IL14 IL15 to IL2 Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3. Note 2: In ...
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Interrupt Source Selector (INTSEL) Each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the interrupt latch only when it is selected in the INTSEL register. The interrupt controller does not hold ...
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Interrupt Sequence 1-machine cycle Interrupt request Interrupt latch (IL) IMF Execute Execute instruction instruction a − Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is ...
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Using PUSH and POP instructions If only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the PUSH/POP instructions. Example :Save/store register using PUSH and POP instructions PINTxx: PUSH ...
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Interrupt Sequence Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing 3.4.3 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows. As for address trap interrupt (INTATRAP required to alter ...
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Note recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return inter- rupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example 2). Note 2: When the ...
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External Interrupts Source Pin INT0 INT0 INT1 INT1 INT2 INT2 INT3 INT3 INT4 INT4 INT5 INT5 Note 1: In NORMAL1/2 or IDLE1/2 mode signal with no noise is input on an external interrupt pin, it takes a ...
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External Interrupt Control Register EINTCR (0037H) INT1NC INT0EN INT4ES INT1NC Noise reject time select INT0EN P00/ pin configuration INT0 INT4 ES INT4 edge select INT3 ES INT3 edge select INT2 ES INT2 edge select INT1 ES INT1 ...
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External Interrupts Page 44 TMP86FH46ANG ...
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Special Function Register (SFR) The TMP86FH46ANG adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address ...
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SFR Address 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH Note 1: Do not access reserved areas by the program. Note ...
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DBR Address 0F80H : : 0F9FH Address 0FA0H : : 0FBFH Address 0FC0H : : 0FDFH Address 0FE0H 0FE1H 0FE2H 0FE3H 0FE4H 0FE5H 0FE6H 0FE7H 0FE8H 0FE9H 0FEAH 0FEBH 0FECH 0FEDH 0FEEH 0FEFH 0FF0H 0FF1H 0FF2H 0FF3H 0FF4H 0FF5H ...
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DBR Note 2: − ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 48 ...
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Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). 5.1 Time Base Timer 5.1.1 Configuration MPX 23 15 fc/2 or fs/2 21 ...
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Time Base Timer Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt fre- quency must not be changed with the disable from the enable state.) Both frequency selection and enabling ...
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Divider Output ( DVO Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from 5.2.1 Configuration Output latch D Q Data output MPX ...
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Divider Output (DVO) Example :1.95 kHz pulse output (fc = 16.0 MHz) Table 5-2 Divider Output Frequency ( Example : fc = 16.0 MHz 32.768 kHz ) DVOCK LD (TBTCR) , 00000000B LD (TBTCR) , 10000000B Divider ...
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Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spu- rious noises or the deadlock conditions, and return the CPU to a system recovery routine. The ...
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Watchdog Timer Control 6.2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watch- dog timer is automatically enabled after the reset release. 6.2.1 Malfunction Detection Methods Using the Watchdog ...
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Watchdog Timer Control Register WDTCR1 (0034H) (ATAS) WDTEN Watchdog timer enable/disable Watchdog timer detection time WDTT [s] WDTOUT Watchdog timer output select Note 1: After clearing WDTOUT to “0”, the program cannot set it to “1”. ...
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Watchdog Timer Control 6.2.3 Watchdog Timer Disable To disable the watchdog timer, set the register in accordance with the following procedures. Setting the reg- ister in other procedures causes a malfunction of the microcontroller. 1. Set the interrupt master ...
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Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1<WDTOUT> is set to “1”, a watchdog timer reset request is generated. When a watchdog timer reset request is generated, the nal and the internal hardware is reset. The reset ...
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Address Trap 6.3 Address Trap The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address traps. Watchdog Timer Control Register WDTCR1 (0034H) Select address trap generation in ATAS ...
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Address Trap Reset While WDTCR1<ATOUT> is “1”, if the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (while WDTCR1<ATAS> is “1”), DBR or the ...
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Address Trap Page 60 TMP86FH46ANG ...
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I/O Ports The TMP86FH46ANG have 5 parallel input/output ports (33 pins) as follows. Primary Function Port P0 8-bit I/O port Port P1 6-bit I/O port Port P2 3-bit I/O port Port P3 8-bit I/O port Port P4 8-bit I/O ...
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Port P0 (P07 to P00) 7.1 Port P0 (P07 to P00) Port 8-bit input/output port which is also used as an external interrupt input, Serial PROM mode control input, serial interface input/output and timer/counter input/output. When ...
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Port P1 (P15 to P10) Port 6-bit input/output port which can be configured as an input or an output in one-bit unit under software control. Input/output mode is specified by the corresponding bit in the port ...
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Port P2 (P22 to P20) 7.3 Port P2 (P22 to P20) Port 3-bit input/output port also used as an external interrupt, a STOP mode release signal input, and low-frequency crystal oscillator con- nection pins. ...
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Port P3 (P37 to P30) Port 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. Port P3 is also used as an analog input, key on ...
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Port P4 (P47 to P40) 7.5 Port P4 (P47 to P40) Port 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. Input/output mode is specified by ...
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TimerCounter 1 (TC1) 8.1 Configuration Figure 8-1 TimerCounter 1 (TC1) Page 67 TMP86FH46ANG ...
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TimerCounter Control 8.2 TimerCounter Control The TimerCounter 1 is controlled by the TimerCounter 1 control register (TC1CR) and two 16-bit timer registers (TC1DRA and TC1DRB). Timer Register 15 14 TC1DRA (0011H, 0010H) TC1DRB (0013H, 0012H) TimerCounter 1 Control Register ...
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Note 4: Auto-capture can be used only in the timer, event counter, and window modes. Note 5: To set the timer registers, the following relationship must be satisfied. TC1DRA > TC1DRB > 1 (PPG output mode), TC1DRA > 1 (other ...
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Function 8.3 Function TimerCounter 1 has six types of operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output modes. 8.3.1 Timer mode In the timer mode, the up-counter counts up using the ...
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Timer start Source clock Counter 0 1 TC1DRA ? INTTC1 interruput request Source clock m − − 1 Counter m − 1 TC1DRB ? ACAP1 Figure 8-2 Timer Mode Timing Chart n − ...
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Function 8.3.2 External Trigger Timer Mode In the external trigger timer mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. For the trigger edge ...
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Count start TC1 pin input Source clock Up-counter TC1DRA INTTC1 interrupt request Count start TC1 pin input Source clock Up-counter TC1DRA INTTC1 interrupt request Figure 8-3 External Trigger Timer Mode Timing Chart ...
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Function 8.3.3 Event Counter Mode In the event counter mode, the up-counter counts up at the edge of the input pulse to the TC1 pin. Either the rising or falling edge of the input pulse is selected as the ...
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Window Mode In the window mode, the up-counter counts up at the rising edge of the pulse that is logical ANDed product of the input pulse to the TC1 pin (window pulse) and the internal source clock. Either the ...
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Function 8.3.5 Pulse Width Measurement Mode In the pulse width measurement mode, the up-counter starts counting by the input pulse triggering of the TC1 pin, and counts up at the edge of the internal clock. Either the rising or ...
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Example :Duty measurement (resolution fc/2 CLR LD DI SET PINTTC1: CPL JRS RETI SINTTC1 RETI : VINTTC1: DW TC1 pin INTTC1 interrupt request INTTC1SW 7 [Hz]) (INTTC1SW INTTC1 ...
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Function Count start TC1 pin input Internal clock Counter TC1DRB INTTC1 interrupt request Count start TC1 pin input Internal clock Counter TC1DRB INTTC1 interrupt request Trigger (a) Single-edge capture 0 1 ...
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Programmable Pulse Generate (PPG) Output Mode In the programmable pulse generation (PPG) mode, an arbitrary duty pulse is generated by counting per- formed in the internal clock. To start the timer, TC1CR<TC1S> specifies either the edge of the input ...
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Function Example :Generating a pulse which is high-going for 800 µs and low-going for 200 µs ( MHz) LD LDW LDW LD Example :After stopping PPG, setting the PPG pin to a high-level to restart PPG (fc ...
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Timer start Internal clock Counter TC1DRB n Match detect TC1DRA m PPG pin output INTTC1 interrupt request Count start TC1 pin input Trigger Internal clock Counter TC1DRB m TC1DRA PPG pin output ...
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Function Page 82 TMP86FH46ANG ...
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TimerCounter (TC3, TC4) 9.1 Configuration 11 3 fc fc/2 16-bit mode G fc TC4 pin H S TC4M ...
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Configuration 9.2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TTREG3, PWREG3). TimerCounter 3 Timer Register TTREG3 7 6 (0018H) R/W PWREG3 7 6 (001AH) R/W Note 1: ...
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Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 9- 3. Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the ...
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Configuration The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and two 8-bit timer registers (TTREG4 and PWREG4). TimerCounter 4 Timer Register TTREG4 7 6 (0019H) R/W PWREG4 7 6 (001BH) R/W Note 1: Do not ...
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Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC3CR<TC3CK>. Set the timer start control and timer F/F control by programming TC4S and TFF4, respectively. Note 7: The operating clock settings are limited depending ...
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Configuration Table 9-3 Constraints on Register Values Being Compared Operating mode 8-bit timer/event counter 8-bit PDO 8-bit PWM 16-bit timer/event counter Warm-up counter 16-bit PWM 16-bit PPG Note Register Value 1≤ (TTREGn) ≤255 1≤ ...
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Function The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8- bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16- ...
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Configuration TC4CR<TC4S> Internal Source Clock Counter TTREG4 ? INTTC4 interrupt request 9.3.2 8-Bit Event Counter Mode (TC3 the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj ...
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Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift ...
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Configuration Figure 9-4 8-Bit PDO Mode Timing Chart (TC4) Page 92 TMP86FH46ANG ...
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Pulse Width Modulation (PWM) Output Mode (TC3, 4) This mode is used to generate a pulse-width modulated (PWM) signals with bits of resolution. The up-counter counts up using the internal clock. When a match between ...
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Configuration Figure 9-5 8-Bit PWM Mode Timing Chart (TC4) Page 94 TMP86FH46ANG ...
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Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascad- able to form a 16-bit timer. When a match between the up-counter and the ...
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Configuration 9.3.6 16-Bit Event Counter Mode (TC3 and 4) In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3 and 4 are cascadable to form a 16-bit event counter. ...
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CLR (TC4CR).3: Stops the timer. CLR (TC4CR).7 : Sets the Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered with- out stopping of the timer when fc, ...
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Configuration Figure 9-7 16-Bit PWM Mode Timing Chart (TC3 and TC4) Page 98 TMP86FH46ANG ...
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Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascad- able to enter the 16-bit PPG mode. The ...
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Configuration Figure 9-8 16-Bit PPG Mode Timing Chart (TC3 and TC40) Page 100 TMP86FH46ANG ...
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Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a 16-bit ...
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Configuration 9.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 → SLOW2 → NORMAL2 → NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation sta- bility is obtained. Before starting the timer, ...
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Synchronous Serial Interface (SIO) The serial interfaces connect to an external device via SI, SO, and When these pins are used as serial interface, the output latches for each port should be set to "1". 10.1 Configuration Internal data ...
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Control 10.2 Control The SIO is controlled using the serial interface control register (SIOCR1). The operating status of the serial inter- face can be inspected by reading the status register (SIOCR1). Serial Interface Control Register SIOCR1 7 6 (0026H) ...
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Serial Interface Status Register SIOSR (0027H) SIOF SEF TXF Serial transfer operation status SIOF monitor SEF Number of clocks monitor TXF Transmit buffer empty flag RXF Receive buffer full flag TXERR Transfer operation error flag RXERR Receive ...
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Function 10.3 Function 10.3.1 Serial clock 10.3.1.1 Clock source The serial clock can be selected by using SIOCR1<SCK>. When the serial clock is changed, the writing instruction to SIOCR1<SCK> should be executed while the transfer is stopped (when SIOSR<SIOF> ...
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External clock When an external clock is selected by setting SIOCR1<SCK> to “111B”, the clock via the from an external source is used as the serial clock. To ensure shift operation, the serial clock pulse width must be 4/fc ...
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Function 10.3.2 Transfer bit direction Transfer data direction can be selected by using SIOCR1<SIODIR>. The transfer data direction can't be set individually for transmit and receive operations. When the data direction is changed, the writing instruction to SIOCR1<SIODIR> should ...
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LSB receive mode LSB receive mode is selected by setting SIOCR1<SIODIR> to “1”, in which case the data is received sequentially beginning with the least significant bit (Bit0). 10.3.2.3 Transmit/receive mode (1) MSB transmit/receive mode MSB transmit/receive mode are ...
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Function (2) During the transmit operation When data is written to SIOTDB, SIOSR<TXF> is cleared to “0”. In internal clock operation, in case a next transmit data is not written to SIOTDB, the serial clock stops to “H” level ...
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SIOCR1<SIOS> SIOSR<SIOF> Start shift operation SIOSR<SEF> pin SCK SO pin SIOSR<TXF> INTSIO interrupt request SIOTDB <SIOS> ...
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Function SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> pin SCK SO pin SIOSR<TXF> SIOSR<TXERR> INTSIO interrupt request SIOTDB A Writing transmit SIOCR1 data A <SIOINH> Figure 10-9 Example of Transmit Error Processingme 10.3.3.2 Receive mode The receive mode is selected by writing “01B” ...
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If received data is not read out from SIORDB receive error occurs immediately after shift opera- tion is finished. Then INTSIO interrupt request is generated after SIOSR<RXERR> is set to “1”. (3) Stopping the receive operation There are two ways ...
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Function SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> pin SCK SI pin SIOSR<RXF> INTSIO interrupt request SIORDB Figure 10-11 Example of External Clock and MSB Receive Mode (4) Receive error processing Receive errors occur on the following situation. To protect SIORDB and the ...
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SIOCR1<SIOS> SIOSR<SIOF> Start shift operation SIOSR<SEF> pin SCK SI pin SIOSR<RXF> SIOSR<RXERR> INTSIO interrupt request SIORDB ...
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Function (2) During the transmit/receive operation When data is written to SIOTDB, SIOSR<TXF> is cleared to “0” and when a data is read from SIORDB, SIOSR<RXF> is cleared to “0”. In internal clock operation, in case of the condition ...
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SIOCR1<SIOS> SIOSR<SIOF> Start shift operation SIOSR<SEF> pin output SCK SO pin pin INTSIO interrupt request SIOSR<TXF> SIOTDB A Writing transmit data A SIOSR<RXF> SIORDB Figure ...
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Function SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> pin output SCK SO pin SI pin INTSIO interrupt request SIOSR<TXF> SIOTDB A Writing transmit data A SIOSR<RXF> SIORDB Figure 10-14 Example of External Clock and MSB Transmit/Receive Mode (4) Transmit/receive error processing Transmit/receive errors ...
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SIOCR1<SIOS> SIOSR<SIOF> Start shift operation SIOSR<SEF> pin output SCK SO pin pin ...
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Function SIOCR1<SIOS> SIOSR<SIOF> SIOSR<SEF> pin output SCK SO pin SI pin INTSIO interrupt request SIOSR<TXF> SIOTDB A Writing transmit data A SIOSR<RXF> SIOSR<RXERR> SIORDB SIOCR1<SIOINH> Figure 10-16 Example of Transmit/Receive (Receive) Error Processing pin SCK SIOSR<SIOF> SO pin Figure ...
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Asynchronous Serial interface (UART ) 11.1 Configuration UART control register 1 UARTCR1 3 2 INTTXD INTRXD S fc/ fc/26 C fc/52 fc/104 fc/208 fc/416 F INTTC3 G H fc/96 Baud rate generator Figure 11-1 ...
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Control 11.2 Control UART is controlled by the UART Control Registers (UARTCR1, UARTCR2). The operating status can be moni- tored using the UART status register (UARTSR). UART Control Register1 7 6 UARTCR1 (0020H) TXE RXE TXE Transfer operation RXE ...
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UART Status Register UARTSR (0020H) PERR FERR OERR RBFL PERR Parity error flag FERR Framing error flag OERR Overrun error flag RBFL Receive data buffer full flag TEND Transmit end flag TBEP Transmit data buffer empty ...
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Transfer Data Format 11.3 Transfer Data Format In UART, an one-bit start bit (Low level), stop bit (Bit length selectable at high level, by UARTCR1<STBT>), and parity (Select parity in UARTCR1<PE>; even- or odd-numbered parity by UARTCR1<EVEN>) are added ...
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Transfer Rate The baud rate of UART is set of UARTCR1<BRG>. The example of the baud rate are shown as follows. Table 11-1 Transfer Rate (Example) BRG 000 001 010 011 100 101 When TC3 is used as the ...
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STOP Bit Length 11.6 STOP Bit Length Select a transmit stop bit length (1 bit or 2 bits) by UARTCR1<STBT>. 11.7 Parity Set parity / no parity by UARTCR1<PE> and set parity type (Odd- or Even-numbered) by UARTCR1<EVEN>. 11.8 ...
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Status Flag 11.9.1 Parity Error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UARTSR<PERR> is set to “1”. The UARTSR<PERR> is cleared to “0” when the RDBUF is read ...
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Status Flag UARTSR<RBFL> RXD pin Shift register RDBUF UARTSR<OERR> INTRXD interrupt Note:Receive operations are disabled until the overrun error flag UARTSR<OERR> is cleared. 11.9.4 Receive Data Buffer Full Loading the received data in RDBUF sets receive data buffer full ...
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TDBUF xxxx ***** 1 1xxxx0 Shift register TXD pin Start UARTSR<TBEP> INTTXD interrupt Figure 11-9 Generation of Transmit Data Buffer Empty 11.9.6 Transmit End Flag When data are transmitted and no data is in TDBUF (UARTSR<TBEP> = “1”), transmit end ...
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Status Flag Page 130 TMP86FH46ANG ...
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AD Converter (ADC) The TMP86FH46ANG have a 10-bit successive approximation type AD converter. 12.1 Configuration The circuit configuration of the 10-bit AD converter is shown in Figure 12-1. It consists of control register ADCCR1 and ADCCR2, converted value ...
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Register configuration 12.2 Register configuration The AD converter consists of the following four registers converter control register 1 (ADCCR1) This register selects the analog channels and operation mode (Software start or repeat) in which to per- form ...
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AD Converter Control Register ADCCR2 (001DH) IREFON DA converter (Ladder resistor) connection IREFON control AD conversion time select ACK (Refer to the following table about the con- version time) Note 1: Always set bit0 in ADCCR2 ...
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Register configuration EOCF ADBF Note 1: The ADCDR2<EOCF> is cleared to "0" when reading the ADCDR1. Therfore, the AD conversion result should be read to ADCDR2 more first than ADCDR1. Note 2: The ADCDR2<ADBF> is set to "1" when ...
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Function 12.3.1 Software Start Mode After setting ADCCR1<AMD> to “01” (software start mode), set ADCCR1<ADRS> to “1”. AD conver- sion of the voltage at the analog input pin specified by ADCCR1<SAIN> is thereby started. After completion of the AD ...
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Function ADCCR1<AMD> AD conversion start ADCCR1<ADRS> Conversion operation Indeterminate ADCDR1,ADCDR2 ADCDR2<EOCF> INTADC interrupt request ADCDR1 ADCDR2 12.3.3 Register Setting 1. Set up the AD converter control register 1 (ADCCR1) as follows: • Choose the channel to AD convert using ...
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Example :After selecting the conversion time 19.5 µ MHz and the analog input channel AIN3 pin, perform AD con- version once. After checking EOCF, read the converted value, store the lower 2 bits in address 0009EH nd store ...
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Analog Input Voltage and AD Conversion Result 12.5 Analog Input Voltage and AD Conversion Result The analog input voltage is corresponded to the 10-bit digital value converted by the AD as shown in Figure 12-4. 3FF H 3FE H ...
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... The internal equivalent circuit of the analog input pins is shown in Figure 12-5. The higher the output impedance of the analog input source, more easily they are susceptible to noise. Therefore, make sure the out- put impedance of the signal source in your design is 5 kΩ or less. Toshiba also recommends attaching a capac- itor external to the chip. ...
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Precautions about AD Converter Page 140 TMP86FH46ANG ...
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Key-on Wakeup (KWU) In the TMP86FH46ANG, the STOP mode is released by not only P20( STOP5) pins. When the STOP mode is released by STOP2 to STOP5 pins, the In details, refer to the following section " 13.2 Control ...
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Function Also, each level of the STOP2 to STOP5 pins can be confirmed by reading corresponding I/O port data register, check all STOP2 to STOP5 pins "H" that is enabled by STOPCR before the STOP mode is startd (Note2,3). ...
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... The parallel PROM mode allows the flash memory to be accessed as a stand-alone flash memory by the program writer provided by the third party. High-speed access to the flash memory is available by control- ling address and data signals directly. For the support of the program writer, please ask Toshiba sales rep- resentative. ...
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Flash Memory Control 14.1 Flash Memory Control The flash memory is controlled via the flash memory control register (FLSCR) and flash memory stanby control resister (FLSSTB). Flash Memory Control Register FLSCR 7 6 (0FFFH) Flash memory command sequence exe- ...
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Transfer the control program of the FLSSTB register to the RAM area. 2. Jump to the RAM area. 3. Disable (DI) the interrupt master enable flag (IMF = “0”). 4. Set FLSSTB<FSTB> to “1”. 5. Execute the user program. ...
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Command Sequence 14.2 Command Sequence The command sequence in the MCU and the serial PROM modes consists of six commands (JEDEC compatible), as shown in Table 14-1. Addresses specified in the command sequence are recognized with the lower 12 ...
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Chip Erase (All Erase) This command erases the entire flash memory in approximately 30 ms. The next command sequence cannot be executed until the erase operation is completed. To check the completion of the erase operation, perform read operations ...
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Toggle Bit (D6) 14.3 Toggle Bit (D6) After the byte program, chip erase, and read protect command sequence is executed, any consecutive attempts to read from the same address is reversed bit 6 (D6) of the data (toggling between ...
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Access to the Flash Memory Area When the write, erase and read protections are set in the flash memory, read and fetch operations cannot be per- formed in the entire flash memory area. Therefore, to perform these operations in ...
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Access to the Flash Memory Area Example :After chip erasure, the program in the RAM area writes data 3FH to address F000H. ; #### Flash Memory Chip erase Process #### sLOOP1: ; #### Flash Memory Write Process #### sLOOP2: ...
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Flash Memory Control in the MCU mode In the MCU mode, write operations are performed by executing the control program in the RAM area. Before execution of the control program, copy the control program into the RAM area or ...
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Access to the Flash Memory Area Example :After sector erasure (E000H-EFFFH), the program in the RAM area writes data 3FH to address E000H. ; #### Flash Memory Sector Erase Process #### sLOOP1: ; #### Flash Memory Write Process #### ...
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Serial PROM Mode 15.1 Outline The TMP86FH46ANG has a 2048 byte BOOTROM (Mask ROM) for programming to flash memory. The BOOTROM is available in the serial PROM mode, and controlled by TEST, BOOT and tion is performed via UART. ...
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Serial PROM Mode Setting 15.3 Serial PROM Mode Setting 15.3.1 Serial PROM Mode Control Pins To execute on-board programming, activate the serial PROM mode. Table 15-2 shows pin setting to activate the serial PROM mode. Note: The BOOT pin ...
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XIN XOUT VSS GND Figure 15-2 Serial PROM Mode Pin Setting Note 1: For connection of other pins, refer to " Table 15-3 Pin Function in the Serial PROM Mode ". 15.3.3 Example Connection for On-Board Writing Figure 15-3 shows ...
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Serial PROM Mode Setting 15.3.4 Activating the Serial PROM Mode The following is a procedure to activate the serial PROM mode. " Figure 15-4 Serial PROM Mode Timing " shows a serial PROM mode timing. 1. Supply power to ...
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Interface Specifications for UART The following shows the UART communication format used in the serial PROM mode. To perform on-board programming, the communication format of the write controller must also be set in the same manner. The default baud ...
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Interface Specifications for UART Table 15-5 Operating Frequency and Baud Rate in the Serial PROM Mode Reference Baud Rate (bps) Baud Rate Modification (Note 3) Data Ref. Fre- Rating quency (MHz) (MHz 1.91 to 2.10 4 3.82 ...
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Operation Command The eight commands shown in Table 15-6 are used in the serial PROM mode. After reset release, the TMP86FH46ANG waits for the matching data (5AH). Table 15-6 Operation Command in the Serial PROM Mode Command Data Operating ...
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Operation Mode 6. Flash memory status output mode The status of the area from FFE0H to FFFFH, and the read protection condition are output as 7-byte code. The external controller reads this code to recognize the flash memory status. ...
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Flash Memory Erasing Mode (Operating command: F0H) Table 15-7 shows the flash memory erasing mode. Table 15-7 Flash Memory Erasing Mode Transfer Data from the External Transfer Byte Controller to TMP86FH46ANG 1st byte Matching data (5AH) 2nd byte - ...
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Operation Mode 2. The 5th byte of the received data contains the command data in the flash memory erasing mode (F0H). 3. When the 5th byte of the received data contains the operation command data shown in Table 15-6, ...
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Flash Memory Writing Mode (Operation command: 30H) Table 15-8 shows flash memory writing mode process. Table 15-8 Flash Memory Writing Mode Process Transfer Data from External Controller Transfer Byte to TMP86FH46ANG 1st byte Matching data (5Ah) 2nd byte - ...
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Operation Mode Description of the flash memory writing mode 1. The 1st byte of the received data contains the matching data. When the serial PROM mode is acti- vated, TMP86FH46ANG (hereafter called device), waits to receive the matching data ...
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After transmitting the checksum, the device waits for the next operation command data. Note 1: Do not write only the ...
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Operation Mode 15.6.3 RAM Loader Mode (Operation Command: 60H) Table 15-9 shows RAM loader mode process. Table 15-9 RAM Loader Mode Process Transfer Bytes 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th ...
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Note error occurs during the reception of a password address or a password string, TMP86FH46ANG stops UART com- munication and enters the halt condition. In this case, initialize TMP86FH46ANG by the serial PROM mode. Description of RAM ...
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Operation Mode 15.6.4 Flash Memory SUM Output Mode (Operation Command: 90H) Table 15-10 shows flash memory SUM output mode process. Table 15-10 Flash Memory SUM Output Process Transfer Bytes 1st byte 2nd byte 3rd byte 4th byte 5th byte ...
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Product ID Code Output Mode (Operation Command: C0H) Table 15-11 shows product ID code output mode process. Table 15-11 Product ID Code Output Process Transfer Data from External Controller Transfer Bytes to TMP86FH46ANG 1st byte Matching data (5AH) 2nd ...
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Operation Mode 5. After sending the checksum, the device waits for the next operation command data. Page 170 TMP86FH46ANG ...
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Flash Memory Status Output Mode (Operation Command: C3H) Table 15-12 shows Flash memory status output mode process. Table 15-12 Flash Memory Status Output Mode Process Transfer Data from External Con- Transfer Bytes troller to TMP86FH46ANG Matching data (5AH) 1st ...
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Operation Mode 15.6.7 Flash Memory Read Protection Setting Mode (Operation Command: FAH) Table 15-13 shows Flash memory read protection setting mode process. Table 15-13 Flash Memory Read Protection Setting Mode Process Transfer Bytes 1st byte 2nd byte 3rd byte ...
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FAH). If the 5th byte does not contain the operation command data, the device enters the halt condition after transmitting 3 bytes of operation command error code (63H). 4. The 7th through m’th bytes of the transmitted and ...
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Error Code 15.7 Error Code When detecting an error, the device transmits the error code to the external controller, as shown in Table 15-14. Table 15-14 Error Code Note password error occurs, TMP86FH46ANG does not transmit an ...
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Calculation data The data used to calculate the checksum is listed in Table 15-15. Table 15-15 Checksum Calculation Data Operating Mode Flash memory writing mode Data in the entire area of the flash memory Flash memory SUM output mode ...
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Intel Hex Format (Binary) 15.9 Intel Hex Format (Binary) 1. After receiving the checksum of a data record, the device waits for the start mark (3AH “:”) of the next data record. After receiving the checksum of a data ...
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RXD pin UART F0H 12H F1H 07H 01H 02H 03H 04H 05H 06H 07H 08H Example PNSA = F012H PCSA = F107H Password string = 01H,02H,03H,04H,05H 06H,07H,08H Figure 15-5 Password Comparison 15.10.1Password String The password string transmitted from the external ...
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Product ID Code 15.11Product ID Code The product ID code is the 13-byte data containing the start address and the end address of ROM. Table 15-17 shows the product ID code format. Table 15-17 Product ID Code Format Data ...
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Flash memory read pro- RPENA tection status The status from FFE0H BLANK to FFFFH. Some operation commands are limited by the flash memory status code 1. If the read protection is enabled, flash memory writing mode command and RAM loader ...
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Specifying the Erasure Area 15.13Specifying the Erasure Area In the flash memory erasing mode, the erasure area of the flash memory is specified by n−2 byte data. The start address of an erasure area is specified by ERASTA, and ...
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Port Input Control Register SPCR (0FEAH) Port input control in the serial PROM PIN mode Note 1: The SPCR register can be read or written only in the serial PROM mode. When the write instruction is executed ...
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Flowchart 15.15Flowchart Page 182 TMP86FH46ANG ...
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Timing Table 15-19 UART Timing-1 (VDD = 4 MHz, Topr = -10 to 40°C) Parameter Time from matching data reception to the echo back Time from baud rate modification data reception ...
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UART Timing Page 184 TMP86FH46ANG ...
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Input/Output Circuitry 16.1 Control Pins The input/output circuitries of the TMP86FH46ANG control pins are shown below. Control Pin I/O XIN Input XOUT Output Osc. enable XTIN Input XTOUT Output I/O RESET Watchdog timer reset TEST Input Note: The TEST ...
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Input/Output Ports 16.2 Input/Output Ports Port I/O P0 I/O P1 I/O P2 I/O P3 I/O P4 I/O Input/Output Circuitry nitial "High-Z" Data output nput from output latch Pin input nitial "High-Z" VDD Data output Disable Pin input nitial "High-Z" ...