TMP86FH46ANG(Z) Toshiba, TMP86FH46ANG(Z) Datasheet - Page 126

• Manufacturer Part Number: TMP86FH46ANG(Z)
• Description: IC MCU 8BIT FLASH 16KB 42-SDIP
• Manufacturer: Toshiba
• Series: TLCS-870/Cr

Specifications of TMP86FH46ANG(Z)

• Core Processor: 870/C
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-SDIP (0.600", 15.24mm)
• Processor Series: TLCS-870
• Core: 870/C
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SIO, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: BMSKTOPAS86FH47(AND), BM1040R0A, BMP86A100010A, BMP86A100010B, BMP86A200010B, BMP86A200020A, BMP86A300010A, BMP86A300020A, BMP86A300030A, SW89CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: BM1401W0A-G - FLASH WRITER ON-BOARD PROGRAMTMP86C909XB - EMULATION CHIP FOR TMP86F SDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: TMP86FH46ANGZ

10.3 Function
SIOSR<TXERR>
SIOTDB
SIOCR1
<SIOINH>
SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK
SO pin
SIOSR<TXF>
INTSIO
interrupt
request
10.3.3.2 Receive mode
pin
Writing transmit
data A
(1)
(2)
The receive mode is selected by writing “01B” to SIOCR<SIOM>.
SIOCR1<SCK>. Transfer direction is selected by using SIOCR1<SIODIR>.
SCK
direction of the bit specified by SBIDIR<SIODIR>.
clock falling edge.
rupt request is generated and SIOSR<RXF> is set to “1”
when the all of the 8-bit data has been received. Automatic-wait function is released by reading a
received data from SIORDB. Then, receive operation is restarted after maximum 1-cycle of serial
clock.
SIORDB, before the next data shift-in operation is finished.
Starting the receive operation
Receive mode is selected by setting “01” to SIOCR1<SIOM>. Serial clock is selected by using
After SIOCR1<SIOS> is set to “1”, SIOSR<SIOF> is set synchronously to “1” the falling edge of
Synchronizing with the
SIOSR<SEF> is kept in high level, between the first clock falling edge of
When 8-bit data is received, the data is transferred to SIORDB from shift register. INTSIO inter-
Note: In internal clock operation, when the SIOCR1<SIOS> is set to "1", the serial clock is generated
During the receive operation
The SIOSR<RXF> is cleared to “0” by reading a data from SIORDB.
In the internal clock operation, the serial clock stops to “H” level by an automatic-wait function
In external clock operation, after SIOSR<RXF> is set to “1”, the received data must be read from
Figure 10-9 Example of Transmit Error Processingme
A
pin.
from
A7 A6
Writing transmit
data B
SCK
Start shift
operation
pin after maximum 1-cycle of serial clock frequency.
A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0
B
SCK
pin's rising edge, the data is received sequentially from SI pin with the
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Start shift
operation
Start shift
operation
SCK
TMP86FH46ANG
Unknown
pin and eighth