TMP86FH46ANG(Z) Toshiba, TMP86FH46ANG(Z) Datasheet - Page 44

• Manufacturer Part Number: TMP86FH46ANG(Z)
• Description: IC MCU 8BIT FLASH 16KB 42-SDIP
• Manufacturer: Toshiba
• Series: TLCS-870/Cr

Specifications of TMP86FH46ANG(Z)

• Core Processor: 870/C
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-SDIP (0.600", 15.24mm)
• Processor Series: TLCS-870
• Core: 870/C
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SIO, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: BMSKTOPAS86FH47(AND), BM1040R0A, BMP86A100010A, BMP86A100010B, BMP86A200010B, BMP86A200020A, BMP86A300010A, BMP86A300020A, BMP86A300030A, SW89CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: BM1401W0A-G - FLASH WRITER ON-BOARD PROGRAMTMP86C909XB - EMULATION CHIP FOR TMP86F SDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: TMP86FH46ANGZ

2.3 Reset Circuit
Instruction
execution
RESET output
Internal reset
signal
2.3.2 Address trap reset
2.3.3 Watchdog timer reset
2.3.4 System clock reset
Note 1: Address “a” is in the SFR, DBR or on-chip RAM (WDTCR1<ATAS> = “1”) space.
Note 2: During reset release, reset vector “r” is read out, and an instruction at address “r” is fetched and decoded.
Note 3: Varies on account of external condition: voltage or capacitance
from the on-chip RAM (when WDTCR1<ATAS> is set to “1”), DBR or the SFR area, address trap reset will be
generated. The reset time is maximum 24/fc[s] (1.5µs at 16.0 MHz). Then, the
during maximum 24/fc[s].
CPU. (The oscillation is continued without stopping.)
mum 24/fc[s] (1.5µs at 16.0MHz).
If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction
Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alter-
Refer to Section “Watchdog Timer”.
If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the
The reset time is maximum 24/fc (1.5 µs at 16.0 MHz). Then, the
- In case of clearing SYSCR2<XEN> and SYSCR2<XTEN> simultaneously to “0”.
- In case of clearing SYSCR2<XEN> to “0”, when the SYSCR2<SYSCK> is “0”.
- In case of clearing SYSCR2<XTEN> to “0”, when the SYSCR2<SYSCK> is “1”.
native.
JP a
Address trap is occurred
Maximum 24/fc [s]
Figure 2-16 Address Trap Reset
("L" output)
Note 3
Page 30
4/fc to 12/fc [s]
RESET
Reset release
pin outputs "L" level during maxi-
16/fc [s]
RESET
pin outputs "L" level
Instruction at address r
TMP86FH46ANG