TMP86FH46ANG(Z) Toshiba, TMP86FH46ANG(Z) Datasheet - Page 125

• Manufacturer Part Number: TMP86FH46ANG(Z)
• Description: IC MCU 8BIT FLASH 16KB 42-SDIP
• Manufacturer: Toshiba
• Series: TLCS-870/Cr

Specifications of TMP86FH46ANG(Z)

• Core Processor: 870/C
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SIO, UART/USART
• Peripherals: LED, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 42-SDIP (0.600", 15.24mm)
• Processor Series: TLCS-870
• Core: 870/C
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SIO, UART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: BMSKTOPAS86FH47(AND), BM1040R0A, BMP86A100010A, BMP86A100010B, BMP86A200010B, BMP86A200020A, BMP86A300010A, BMP86A300020A, BMP86A300030A, SW89CN0-ZCC, SW00MN0-ZCC
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• For Use With: BM1401W0A-G - FLASH WRITER ON-BOARD PROGRAMTMP86C909XB - EMULATION CHIP FOR TMP86F SDIP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: TMP86FH46ANGZ

SIOCR1<SIOS>
SIOSR<SIOF>
SIOSR<SEF>
SCK
SO pin
SIOSR<TXF>
INTSIO
interrupt
request
SIOTDB <SIOS>
pin
Writing transmit
data A
SCK
SIOSR<SIOF>
SO pin
(4)
Figure 10-7 Exaple of External Clock and MSB Transmit Mode
pin
Transmit error processing
Transmit errors occur on the following situation.
A
Figure 10-8 Hold Time of the End of Transmit Mode
• Shift operation starts before writing next transmit data to SIOTDB in external clock opera-
tion.
If transmit errors occur during transmit operation, SIOSR<TXERR> is set to “1” immedi-
ately after starting shift operation. Synchronizing with the next serial clock falling edge,
INTSIO interrupt request is generated.
If shift operation starts before writing data to SIOTDB after SIOCR1<SIOS> is set to “1”,
SIOSR<TXERR> is set to “1” immediately after shift operation is started and then INTSIO
interrupt request is generated.
SIO pin is kept in high level when SIOSR<TXERR> is set to “1”. When transmit error
occurs, transmit operation must be forcibly stop by writing SIOCR1<SIOINH> to “1”. In
this case, SIOCR1<SIOS>, SIOSR register, SIORDB register and SIOTDB register are ini-
tialized.
A7 A6
Writing transmit
data B
Start shift
operation
A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0
B
Page 111
Writing transmit data
Start shift
operation
Writing transmit
data C
C
4/fc
<
t SODH
t SODH
Start shift
operation
Clearing SIOS
<
8/fc
TMP86FH46ANG