R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1033

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ANBGV

Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ANBGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
• MC Operating Mode:
• Coded Block Pattern (cbp):
Writing Order
Command
parameter 1
Command
parameter 2
Command
parameter 3
Command
parameter 4
Command
parameter 5
Command
parameter 6
Command
parameter 7
Command
parameter 8
⎯ Bits 2 to 0 are H'0: Intra macroblock processing
⎯ Bits 2 to 0 are H'1: Forward macroblock processing
⎯ Bits 2 to 0 are H'2: Reverse macroblock processing
⎯ Bits 2 to 0 are H'3: Bidirectional macroblock processing
⎯ Bits 2 to 0 are H'4: End command (When bit 2 is 1, it is regarded as the end command.)
⎯ Bit 31: Indicates whether or not the Y0 IDCT data exists (0: IDCT data is invalid, 1: IDCT
⎯ Bit 30: Indicates whether or not the Y1 IDCT data exists (0: IDCT data is invalid, 1: IDCT
⎯ Bit 29: Indicates whether or not the Y2 IDCT data exists (0: IDCT data is invalid, 1: IDCT
⎯ Bit 28: Indicates whether or not the Y3 IDCT data exists (0: IDCT data is invalid, 1: IDCT
⎯ Bit 27: Indicates whether or not the U IDCT data exists (0: IDCT data is invalid, 1: IDCT
data is valid)
data is valid)
data is valid)
data is valid)
data is valid)
Intra Macroblock
Processing
Bits 31 to 26: cbp
Bits 2 to 0: H'0
mbcol
mbrow
Buffer RAM
pointer
Forward
Macroblock
Processing
Bits 31 to 26: cbp
Bits 2 to 0: H'1
mbcol
mbrow
Forward_
Recon_down
Forward_
Recon_right
Buffer RAM
pointer
Reverse
Macroblock
Processing
Bits 31 to 26: cbp
Bits 2 to 0: H'2
mbcol
mbrow
Back_
Recon_down
Back_
Recon_right
Buffer RAM
pointer
20. Graphics Data Translation Accelerator (GDTA)
Rev.1.00 Jan. 10, 2008 Page 1001 of 1658
Bidirectional
Macroblock
Processing
Bits 31 to 26: cbp
Bits 2 to 0: H'3
mbcol
mbrow
Forward_
Recon_down
Forward_
Recon_right
Back_
Recon_down
Back_
Recon_right
Buffer RAM
pointer
End
Command
Bits 2 to 0: H'4
REJ09B0261-0100
MC
command

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