R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1380

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

27. NAND Flash Memory Controller (FLCTL)
Note:
27.3.3
FLCMCDR is a 32-bit readable/writable register that specifies a command to be issued in
command access or sector access.
Rev.1.00 Jan. 10, 2008 Page 1348 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
16
15 to 0
Bit
31 to 16
15 to 8
7 to 0
R/W:
R/W:
Bit:
Bit:
*
Command Code Register (FLCMCDR)
Bit Name
DOCMD1
SCTCNT
[15:0]
Bit Name
—
CMD[15:8] H'00
CMD[7:0]
For command stage, address stage, and data stage, see figure 27.2.
R/W
31
15
R
0
0
R/W
30
14
R
0
0
R/W
29
13
Initial
Value
0
H'0000
Initial
Value
All 0
H'00
R
0
0
R/W
CMD[15:8]
28
12
R
0
0
R/W
R/W
R/W
R/W
27
11
R/W
R
R/W
R/W
R
0
0
R/W
26
10
R
0
0
Description
First Command Stage* Execution Specification
Specifies whether the first command stage* is executed
in command access mode.
0: Does not execute the first command stage
1: Executes the first command stage
Sector Transfer Count Specification
Specify the number of sectors to be read continuously
in sector access mode. These bits are counted down for
each sector transfer end, and stop when they reach 0.
When accessing one sector, set SCTCNT to 1.
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Specify a command code to be issued in the second
command stage.
Specify a command code to be issued in the first
command stage.
R/W
25
R
0
9
0
R/W
24
R
0
8
0
R/W
23
R
0
7
0
R/W
22
R
0
6
0
R/W
21
R
5
0
0
R/W
20
R
0
4
CMD[7:0]
0
R/W
19
R
0
3
0
R/W
18
R
0
2
0
R/W
17
R
0
1
0
R/W
16
R
0
0
0