R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1229

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

24.3.11 Command Type Register (CMDTYR)
CMDTYR is an 8-bit readable/writable register that specifies the command format in conjunction
with RSPTYR. Bits TY1 and TY0 specify the existence and direction of transfer data, and bits
TY6 to TY2 specify the additional settings. All of bits TY6 to TY2 should be cleared to 0 or only
one of them should be set to 1. Bits TY6 to TY2 can only be set to 1 if the corresponding settings
in TY1 and TY0 allow that setting. If these bits are not set correctly, the operation cannot be
guaranteed. When executing a single block transaction, set TY1 and TY0 to 01 or 10, and TY6 to
TY2 to all 0s.
Bit
7 to 5
6
5
4
Bit Name
⎯
TY6
TY5
TY4
Initial value:
Initial
Value
All 0
0
0
0
R/W:
Bit:
⎯
7
0
R
R/W
R
R/W
R/W
R/W
TY6
R/W
6
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Type 6
Specifies a predefined multiple block transaction.
TY[1:0] should be set to 01 or 10.
When using the command set to this bit, it is necessary
to specify the transfer block size and the transfer block
number in the TBCR and TBNCR respectively.
Type 5
Specifies a multiple block transaction when using
secure MMC. TY[1:0] should be set to 01 or 10.
Using the command to set to this bit, it is necessary to
specify the transfer block size and the transfer block
number in the TBCR and TBNCR respectively.
Type 4
Set this bit to 1 when specifying the CMD12 command.
Bits TY1 and TY0 should be set to 00.
R/W
TY5
5
0
TY4
R/W
4
0
R/W
TY3
3
0
Rev.1.00 Jan. 10, 2008 Page 1197 of 1658
TY2
R/W
2
0
24. Multimedia Card Interface (MMCIF)
TY1
R/W
1
0
R/W
TY0
0
0
REJ09B0261-0100