R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1673

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ANBGV

Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ANBGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Legend:
⎯:
(m):
(s):
I:
O:
H:
L:
Z:
PI:
PZ:
K:
POR: Power-on reset
Notes: 1. Depends on the MODE9 pin setting.
Pin Name
(LSI level)
SCIF5_SCK/
HAC1_SDOUT/
SSI1_SDATA
ASEBRK/
BRKACK
TCK
TRST
TDI
TMS
TDO
AUDCK
AUDSYNC
AUDATA[3:0]
MPMD
Disabled (not selected) or not supported
LBSC master mode
LBSC slave mode
Input
Output
High level output
Low level output
High impedance state
Input and pulled up with a built-in pull-up resistance.
High impedance and pulled up with a built-in pull-up resistance.
Retain the previous pin state.
2. After power-or reset, this pin is output state. Must not input signals immediately after
3. Depends on the settings of the MODE[12:11] pin and corresponding registers.
4. When the bus mode selected by MODE11/MODE12 pins is PCI host bus bridge or
power-on reset.
PCIC normal (non-host), clock must be input to PCICLK pin. When the bus mode
selected by MODE11/MODE12 pins is local bus or display unit, PCICLK pin must be
pulled-up to VDDQ or pulled-down to GND.
Pin Name
(Module level)
Port N6
(default)
SCIF5_SCK
HAC1_SDOUT
SSI1_SDATA
ASEBRK/
BRKACK
TCK
TRST
TDI
TMS
TDO
AUDCK
AUDSYNC
AUDATA[3:0]
MPMD
Related
Module
GPIO
SCIF
HAC
SSI
H-UDI
H-UDI
H-UDI
H-UDI
H-UDI
H-UDI
H-UDI
H-UDI
H-UDI
H-UDI
I/O
I/O
I/O
O
I/O
I/O
I
I
I
I
O
O
O
O
I
Power
-on
PI
PI
PI
PI
PI
PI
O
O
O
O
I
Reset
Rev.1.00 Jan. 10, 2008 Page 1641 of 1658
Manual Sleep
K
I
O
I
PI
PI/O
PI
PI
PI
O
O
O
O
I
K
K
O
K
PI/O
PI
PI
PI
PI
O
O
O
O
I
Module
Standby
K
O
K
PI
PI
PI
PI
O
REJ09B0261-0100
Bus
Release
K
K
O
K
PI/O
PI
PI
PI
PI
O
O
O
I
O
Appendix

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