R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1171

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

22.4.7
Set each register after setting the PFC.
(1)
Figure 22.9 shows an example of settings and operation for master mode transmission.
Note: * When interrupts due to transmit data underflow are enabled, after setting the no. 6 transmit data, the TXE bit should be set to 1.
Transmission in Master Mode
No.
1
2
3
4
5
6
7
8
Transmit and Receive Procedures
Set the FSE and TXE bits in SICTR to 1
Transmit SITDR from SIOF_TXD
synchronously with SIOF_SYNC
Figure 22.9 Example of Transmit Operation in Master Mode
Set the SCKE bit in SICTR to 1
Set SIMDR, SISCR, SITDAR,
Set the TXE bit in SICTR to 0
SIRDAR, SICDAR, SITCR,
Start SIOF_SCK output
Transfer ended?
and SIFCTR
TDREQ = 1
Set SITDR
Flowchart
Start
End
Yes
Yes
No
No
Set operating mode, serial clock, slot
positions for transmit/receive data, slot
position for control data, and FIFO
request threshold value
Set operation start for baud rate generator
Set the start for frame synchronous signal
output and enable transmission
Set transmit data
Set to disable transmission
SIOF Settings
Rev.1.00 Jan. 10, 2008 Page 1139 of 1658
22. Serial I/O with FIFO (SIOF)
Output serial clock
Output frame
synchronous signal and
issue transmit transfer
request*
Transmit
End transmission
SIOF Operation
REJ09B0261-0100