R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1210

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

24. Multimedia Card Interface (MMCIF)
(2)
24.3.2
CMDSTRT is an 8-bit readable/writable register that triggers the start of command transmission,
representing the start of a command sequence. The following operations should have been
completed before the command sequence starts.
• Analysis of prior command response, clearing the command response register write if
• Analysis/transfer of receive data of prior command if necessary
• Preparation of transmit data of the next command if necessary
• Setting of CMDTYR, RSPTYR, TBCR and TBNCR
• Setting of CMDR0 to CMDR4
Command sequences are controlled by the sequencers in both the MMCIF side and the MMC card
side. Normally, these operate synchronously. However, if an error occurs or a command is
aborted, these may become temporarily unsynchronized. Be careful when setting the CMDOFF bit
in OPCR, issuing the CMD12 command, or processing an error in MMC mode. A new command
sequence should be started only after the end of the command sequence on both the MMCIF and
card sides is confirmed. See section24.4, Operation when an error occurred.
Rev.1.00 Jan. 10, 2008 Page 1178 of 1658
REJ09B0261-0100
Bit
7 to 1
0
necessary
The CMDR0 to CMDR4, CMDTYR, RSPTYR, TBCR and TBNCR registers should not be
changed until command transmission has ended (during the CWRE flag in CSTR has been set
to 1 or until command transmit end interrupt has occurred).
CMDR5
Command Start Register (CMDSTRT)
Bit Name
CRC
End
Initial value:
Initial
Value
All 0
0
R/W:
Bit:
R
7
0
R/W
R
R
6
0
R
Description
These bits are always read as 0. The write value should
always be 0.
This bit is always read as 0. The write value should
always be 0.
R
5
0
CRC
4
0
R
R
0
3
2
0
R
R
1
0
End
R
0
0