R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 762

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

14. Direct Memory Access Controller (DMAC)
14.6
Note the following things in using this DMAC.
14.6.1
When the DMAC is operating, it is prohibited to set or clear the corresponding bit of MSTPCR1
that controls H-UDI, UBC, DMAC and GDTA modules operation, and also prohibited to change
any frequencies regarding the operation of this LSI. Operation is not guaranteed if these are
performed.
Check that the DME bits (bit 0) in both DMAOR0 and DMAOR1 are 0 or the TE bits in CHCR0
to CHCR11 are all 1 before stopping modules by MSTPCR1.
14.6.2
When a DMA address error is occurred, set registers of all channels of corresponding DMAOR*
again and then start a transfer.
Note: Set registers of channels 0 to 5 again when the AE bit of DMAOR0 is set to 1, and set
14.6.3
When a NMI interrupt is occurred, DMA transfer is stopped. Set registers of all channels again
after returning from the exception handling routine of a NMI and then start a transfer.
14.6.4
During a burst mode transfer, do not make a transition to sleep mode until the transfer of
corresponding channel has been completed.
14.6.5
When 16- or 32-byte transfer is performed in 8-, 16-, 32-, or 64-bit bus width, longword transfer is
performed in 8- or 16-bit bus width, or word transfer is performed in 8-bit bus width, DMA
transfer units are divided into multiple bus cycles. Note that DACK output is divided-up, like CS,
if DMA transfer size is divided into multiple bus cycles and CS is negated between bus cycles.
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registers of channels 6 to 11 again when the AE bit of DMAOR1 is set to 1.
Usage Notes
Stopping Modules and Changing Frequency
Address Error
NMI Interrupt
Burst Mode Transfer
Divided-Up DACK Output