R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 570

IC SUPERH MPU ROMLESS 436-BGA

R8A77850ANBGV

Manufacturer Part Number
R8A77850ANBGV
Description
IC SUPERH MPU ROMLESS 436-BGA
Manufacturer
Renesas Electronics America
Series
SuperH® SH7780r
Datasheet

Specifications of R8A77850ANBGV

Core Processor
SH-4A
Core Size
32-Bit
Speed
600MHz
Connectivity
Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
Peripherals
DMA, POR, WDT
Number Of I /o
108
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1 V ~ 1.2 V
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
436-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R8A77850ANBGV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
12. DDR2-SDRAM Interface (DBSC2)
Figure 12.15 shows a case in which the pages for both of banks A and B are closed, the page for
bank C is open, and a page hit has occurred. When the tRRD time constraint has been satisfied
starting from issue of the ACT command for bank A, the ACT command for bank B is issued.
Because time tRCD has elapsed from the issue of the ACT command for bank A, a READ
command can be used. The READ command has a burst length of 4, so after two cycles a READ
command for bank B can be issued. A further two cycles later, a READ command for bank C can
be issued. However, the next request is access for which bank C must be closed, and so after the
elapse of time tRTP a PRE command is issued.
Rev.1.00 Jan. 10, 2008 Page 538 of 1658
REJ09B0261-0100
Example of CL = 3
MCK0,
MCK1
MCKE
MCS
MRAS
MCAS
MWE
MA[14:11]
MA[9:0]
MA[10]
MBA[2:0]
MDQS[3:0]
MDM[3:0]
MDQ[31:0]
SDRAM
command
bank A
ACT
Valid
Valid
Valid
Invalid
Invalid
Invalid
tRRD
= 2 cycles
bank B
ACT
Valid
Valid
Valid
High level
bank A
READ
Figure 12.15 tRRD and tRTP
Valid
Valid
Valid
Invalid
Invalid
Invalid
Invalid
bank B
READ
Valid
Valid
Valid
Invalid
Invalid
Invalid
Invalid
bank C
READ
Valid
Valid
Valid
Read data
Invalid
Invalid
tRTP
= 2 cycles
bank C
PRE
Valid
Invalid
Invalid
Invalid
bank C
ACT
Valid
Valid
Valid
Invalid
Invalid
Invalid
Invalid

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