R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 814

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

17. Power-Down Mode
Table 17.1 States of Power-Down Modes
Notes: 1. The TMU, SCIF, SIOF, HSPI, MMCIF, HAC, SSI, FLCTL and UBC should be in module
Rev.1.00 Jan. 10, 2008 Page 782 of 1658
REJ09B0261-0100
Power-
Down
Mode
Sleep
mode
Deep
sleep
mode
Module
standby
function
DDR2-
SDRAM
power
supply
backup *
2
2. Power supplies (1.1 V, 3.3 V) except the 1.8 V power supply are stopped in DDR2-
3. For details on auto-refresh and self-refresh operation, see section 12, DDR2-SDRAM
Conditions of
Transition
SLEEP
instruction
executed (see
section 17.4)
Corresponding
bit in MSTPCR
set to 1 (see
section 17.3.2)
Clear the
corresponding
bits in
MSTPCR0 and
MSTPCR1 to 0
(see sections
17.3.2 and
17.3.3)
See section
17.7
stop state by using the module standby function before execute the SLEEP instruction
to make transition to deep sleep mode. For detail, refer to section 17.5, Deep Sleep
Mode.
SDRAM power supply backup mode. Therefore, all circuitry other than the pad of DDR2
interface are stopped, including DDR2 interface control unit, and the contents of
registers are not retained.
Interface (DBSC2).
CPG
Operate
Operate
Operate
Stopped
CPU
Stopped
(contents
of registers
retained)
Stopped
(contents
of registers
retained)
Operate
Stopped
On-Chip
Memory
Retained
Retained
Retained
Undefined Stopped
DMAC
Operate
Stopped
(contents
of
registers
retained)
Stopped
in six-
channel
units:
channels
0 to 5 and
channels
6 to 11.
On-Chip Peripheral Module
Operate
Stopped
(contents
of
registers
retained)
Stopped
Stopped
GDTA
State
Others
Operate
Operate
(DU,
TMU,
SCIF,
SIOF,
HSPI,
MMCIF,
HAC,
SSI,
FLCTL,
and UBC
are
stopped
*
Specified
modules
stopped
Stopped
1
)
Pin
Operation
retained
Operation
retained
Operation
retained
Undefined
except for the
1.8-V power
supply
interface
(When the
MBKPRST is
low level input,
the MCKE is
high level
output)
DDR2-SDRAM
Auto-refresh or
self-refresh*
Self-refresh
Auto-refresh or
self-refresh
Self-refresh
3
Releasing
Methods
1. Interrupt
2. Power-on
3. Manual
1. Interrupt
2. Power-on
3. Manual
Clear the
corresponding
bits in
MSTPCR0 and
MSTPCR1 to 0
(see sections
17.3.2 and
17.3.3)
Power-on
reset
reset
reset
reset
reset