R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 1497

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

29.2.3
CAR0 and CAR1 are readable/writable 32-bit registers specifying the virtual address to be
included in the break conditions for channels 0 and 1, respectively.
• CAR0
• CAR1
Bit
31 to 0
Bit
31 to 0
Initial value :
Initial value :
Initial value :
Initial value :
R/W:
R/W:
R/W:
R/W:
Bit :
Bit :
Bit :
Bit :
Match Address Setting Registers 0 and 1 (CAR0 and CAR1)
Bit Name
CA
Bit Name
CA
R/W
R/W
R/W
R/W
31
15
31
15
R/W
R/W
R/W
R/W
30
14
30
14
R/W
R/W
R/W
R/W
Initial
Value
Undefined
Initial
Value
Undefined
29
13
29
13
R/W
R/W
R/W
R/W
28
12
28
12
R/W
R/W
R/W
R/W
27
11
27
11
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
26
10
26
10
Compare Address
Specifies the address to be included in the break
conditions.
When the operand bus has been specified using the
CBR0 register, specify the SAB address in CA[31:0].
Description
Description
Compare Address
Specifies the address to be included in the break
conditions.
When the operand bus has been specified using the
CBR1 register, specify the SAB address in CA[31:0].
R/W
R/W
R/W
R/W
25
25
9
9
R/W
R/W
R/W
R/W
24
24
8
8
CA
CA
CA
CA
R/W
R/W
R/W
R/W
23
23
7
7
Rev.1.00 Jan. 10, 2008 Page 1465 of 1658
R/W
R/W
R/W
R/W
22
22
6
6
R/W
R/W
R/W
R/W
21
21
5
5
29. User Break Controller (UBC)
R/W
R/W
R/W
R/W
20
20
4
4
R/W
R/W
R/W
R/W
19
19
3
3
REJ09B0261-0100
R/W
R/W
R/W
R/W
18
18
2
2
R/W
R/W
R/W
R/W
17
17
1
1
R/W
R/W
R/W
R/W
16
16
0
0