R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 628

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

13. PCI Controller (PCIC)
(4)
See section 13.4.3 (2), Accessing PCI Memory Space.
Rev.1.00 Jan. 10, 2008 Page 596 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to 20 LAR
19 to 0
PCI R/W:
PCI R/W:
SH R/W:
SH R/W:
PCI Local Address Register 0 (PCILAR0)
Bit:
Bit:
Bit Name
⎯
R/W
31
15
—
R
R
R
0
0
R/W
30
14
—
R
R
R
0
0
Initial
Value R/W
H'000 SH: R/W
All 0
R/W
29
13
—
R
R
R
0
0
R/W
PCI: R
SH: R
PCI: R
28
12
—
R
R
R
0
0
R/W
27
11
—
R
R
R
0
0
Description
Local Address (12 bits)
These bits specify bits 31 to 20 for the start address of the
local address space 0 (internal bus space in this LSI).
As shown below, the valid bits of LAR change depending on
the local address space size specified by the LSR bit in
PCILSR0.
PCILSR0.LSR ([28:20]) = B'0 0000 0000: Bits [31:20] are valid.
PCILSR0.LSR ([28:20]) = B'0 0000 0001: Bits [31:21] are valid.
PCILSR0.LSR ([28:20]) = B'0 0000 0011: Bits [31:22] are valid.
PCILSR0.LSR ([28:20]) = B'0 0000 0111: Bits [31:23] are valid.
PCILSR0.LSR ([28:20]) = B'0 0000 1111: Bits [31:24] are valid.
PCILSR0.LSR ([28:20]) = B'0 0001 1111: Bits [31:25] are valid.
PCILSR0.LSR ([28:20]) = B'0 0011 1111: Bits [31:26] are valid.
PCILSR0.LSR ([28:20]) = B'0 0111 1111: Bits [31:27] are valid.
PCILSR0.LSR ([28:20]) = B'0 1111 1111: Bits [31:28] are valid.
PCILSR0.LSR ([28:20]) = B'1 1111 1111: Bits [31:29] are valid.
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W
26
10
—
R
R
R
0
0
LAR
R/W
25
—
R
R
R
0
9
0
R/W
24
—
R
R
R
0
8
0
R/W
23
—
R
R
R
0
7
0
R/W
22
—
R
R
R
0
6
0
R/W
21
—
R
R
R
0
5
0
R/W
20
—
R
R
R
0
4
0
19
—
—
R
R
R
R
0
3
0
18
—
—
R
R
R
R
0
2
0
17
—
—
R
R
R
R
0
1
0
16
—
—
R
R
R
R
0
0
0