R8A77850ANBGV Renesas Electronics America, R8A77850ANBGV Datasheet - Page 965

• Manufacturer Part Number: R8A77850ANBGV
• Description: IC SUPERH MPU ROMLESS 436-BGA
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7780r

Specifications of R8A77850ANBGV

• Core Processor: SH-4A
• Core Size: 32-Bit
• Speed: 600MHz
• Connectivity: Audio Codec, MMC, Serial Sound, SCI, SIO, SPI, SSI
• Peripherals: DMA, POR, WDT
• Number Of I /o: 108
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1 V ~ 1.2 V
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 436-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -

19.4.2
All plane display can be turned on and off using the DEN bit in DSYSR. When the DEN bit is 0,
the display data set in DOOR is displayed.
Display is turned on and off for planes 1 to 6 using DPPR. Under the following display conditions,
display data set in BPOR is displayed.
1. When display of all planes 1 to 6 is turned off
2. In an area with no plane for display, due to the display size and display position
3. When the pixels in a plane for display are all a transparent color
Table 19.5 Display On/Off of Plane 1 to 6
Note: Even if display on is set using DPPR, under the following conditions, the setting is handled
Display Plane
Plane 1
Plane 2
Plane 3
Plane 4
Plane 5
Plane 6
as display off, and the corresponding plane is not displayed.
•
•
•
•
•
•
Display On/Off
Planes for which the value set in PnDPXR is greater than the screen size (horizontal
display ending position register (HDE) - horizontal display start position register (HDS))
Planes for which the value set in PnDPYR is greater than the screen size (vertical
display ending position register (VDE) - vertical display start position register (VDS))
Planes for which the value set in PnDSXR is 0
Planes for which the value set in PnDSYR is 0
Planes for which the value set in PnMWR is 0
Planes for which the value set in PnSPXR is equal to or greater than twice the value set
in PnMWR
Display Plane Priority Register (DPPR)
Plane 1 is selected in one among priority positions 1 to 6, and the
corresponding enable bit is set to 1
Plane 2 is selected in one among priority positions 1 to 6, and the
corresponding enable bit is set to 1
Plane 3 is selected in one among priority positions 1 to 6, and the
corresponding enable bit is set to 1
Plane 4 is selected in one among priority positions 1 to 6, and the
corresponding enable bit is set to 1
Plane 5 is selected in one among priority positions 1 to 6, and the
corresponding enable bit is set to 1
Plane 6 is selected in one among priority positions 1 to 6, and the
corresponding enable bit is set to 1
Rev.1.00 Jan. 10, 2008 Page 933 of 1658
19. Display Unit (DU)
REJ09B0261-0100